DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/4/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to for the following reasons:
The specification refers to numeral 116 as a well. In every figure except figures 14, 15, and 17 numeral 116 points to a well. However, in these figures, 116 is pointing to what appears to be the bottom most semiconductor layer of the metal gate stack.
Figure 21: paragraph 43 of the specification says “a hard mask layer 147 is conformally formed on the HK dielectric layer 180 and the gate electrode layer 182.” However, in the figure, it looks like the hard mask 147 has consumed or otherwise taken the place of gate electrode layer 182. Please demarcate the gate electrode layer 182 from the hard mask layer 147.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2021/03343600).
As to claim 11, Chen teaches a semiconductor device structure (fig. 29C), comprising:
a first dielectric wall (280B) disposed over a substrate (206, [0018] and [0031]);
a first transistor (202A) comprising a first plurality of semiconductor layers (220’) vertically stacked over the substrate (206) and disposed at a first side (left) of the first dielectric wall (280B), wherein a first side (right) of each of the first plurality of semiconductor layers (220’) is connected to the first dielectric wall (280B, [0018] and [0047]);
a first gate electrode layer (384A) disposed between two neighboring semiconductor layers of the first plurality of semiconductor layers ([0053]); and
a second dielectric wall (280A) disposed adjacent to and separated from a second side of each of the first plurality of semiconductor layers ([0053]).
As to claims 13-17, the examiner claims different heights of the different dielectric walls. However, any of the wall 280B and 280A can be considered the first and/or second dielectric walls as claimed and still meet the remaining claim limitations. Furthermore, as it pertains to claim 16, the first gate electrode layer (384) is in further contact with the top surface of the second dielectric wall (280B).
Allowable Subject Matter
Claims 1-10 and 18-20 are allowed and claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims.
As to claim 1, Chu (US 2022/0320089) teaches a semiconductor device structure (fig. 26A), comprising:
a dielectric wall (218) disposed over a substrate (202);
first and second metal gate structure portions (200A and 200B) respectively disposed at either side of the dielectric wall (218), wherein each first and second metal gate structure portion (200A and 200B) comprises:
a plurality of semiconductor layers (256A/256B) vertically stacked and separated from each other;
a high-K dielectric layer (262) disposed to surround at least three surfaces of each of the semiconductor layers (256A/256B); and
a gate electrode layer (272) disposed between two neighboring semiconductor layers (256A/B); and
a metal layer (282) disposed on two opposing sidewalls of the dielectric wall 218).
Chu only shows a gate electrode layer (272) on the first metal gate structure portion (200a), and not on the second metal gate structure (200B). Layer 272 of Chu is an n-type work function layer for the NMOS device 200A ([0078]). Metal layer 282 functions as the p-type work function layer, thus there would be no motivation to add a gate electrode layer to the second metal gate structure portion as it already has a work function layer.
As to claim 12, Chen teaches the liner (272, [0031]) and the high-k dielectric (382, [0050]) layers but fails to teach the cap layer surrounding the plurality of semiconductor layers and in contact with the liner, wherein each of the first plurality of semiconductor layers is connected to the first dielectric wall through the cap layer and the liner; and a high-K dielectric in contact with the first dielectric wall, the liner, and the cap layer.
As to claim 18, Chu teaches method for forming a semiconductor device structure, comprising: forming a first fin structure, a second fin structure, and a third fin structure from a substrate (200A and 200B, [0021], although only two are shown, many more are anticipated), wherein the second fin structure is disposed between the first and third fin structures, and
each first, second, and third fin structure comprises a plurality of first semiconductor layers (208) and a plurality of second semiconductor layers (206) alternatingly stacked (fig. 4);
forming a first dielectric wall (218) between the second and third fin structures (fig. 6);
removing the second semiconductor layers (206) from the first, second, and third fin structures (200A and 200B and any others) so that the first semiconductor layers (208) of at least first and second fin structures extend outwardly from a first and a second side of the first dielectric wall, respectively (fig. 15A);
filling a space between two neighboring first semiconductor layers of the first, second, and third fin structures with a gate electrode layer (264, fig. 17A);
forming a second dielectric wall between the first and second fin structures (obvious there would be more walls between more fins).
Chu fails to teach recessing the second dielectric wall so that a top surface of the second dielectric wall is at an elevation below a top surface of the first dielectric wall; and forming a metal layer to cover the first and second dielectric walls as well as the first semiconductor layers of the first, second, and third fin structures.
The remaining claims are allowed at least because they depend from allowable independent claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
2/18/26