DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 06/25/2025 is acknowledged.
Claim 37-38 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/25/2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 8-13, and 16-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kazem (PG-PUB 2021/0272873) in view of Kazem ‘218 (PG-PUB 2020/0362218).
Regarding claim 1, Kazem teaches a method comprising:
depositing a thermal interface material at a first layer thickness between a first layer of a circuit assembly and a second layer of the circuit assembly [0036], wherein the thermal interface material comprises an emulsion of liquid metal droplets and polymer [0034]- [0035],
compressing the circuit assembly to decrease the first layer thickness to a second layer thickness [0039], thereby deforming the liquid metal droplets and increasing the aspect ratio of the particles [0039]-[0040], such that the second layer thickness is no greater than the average particle size of the liquid metal droplets in thermal interface material prior to compressing the circuit assembly [0040],
wherein the second layer thickness can be in the range of 15 microns to 150 microns [0043],
wherein the average particle size of the metal droplets can be at least 150 microns [0028], and
the first layer thickness can be substantially aligned with the first layer thickness [0040].
Given that the second layer thickness is between 15 microns to 150 microns, and the assembly formed between the die and upper layer are pressed from the first layer thickness to reach the second layer thickness, the first layer thickness would be greater than 15 microns to 150 microns.
Kazem does not explicitly teach wherein the first layer thickness is at least 1.1 times the D90 of the liquid metal droplets prior to compressing the circuit assembly.
Kazem ‘218 teaches a method for synthesizing a thermally conductive and
stretchable elastomer composite comprises mixing liquid metal and soft material ( e.g., elastomer) in a centrifugal or industrial shear mixer under conditions such that the liquid
metal forms microscale liquid metal droplets that are dispersed in the soft elastomer (Figure 2 and 3 and [0025]-[0026]). Kazem ‘218 teaches the sizes of the liquid metal droplets are tightly concentrated (about 80%) in the 12 to 30 micron range (Figure 4A-4B using Ecoflex 00-30 and [0027]) and in the 4 to 15 micron range (Figure 5A-5B using Dragon Skin 10 Slow and [0027]). Kazem ‘218 teaches the maximum particle size for the Figure 4A-4B embodiment and Figure 5A-5B embodiment are about 46 to 48 microns and 20 microns, respectively (Figures 4C and 5C). Accordingly, the D90 of the liquid metal droplets of the two embodiments would be greater than 30 microns and less than 48 microns for the Ecoflex embodiment and greater than 15 and less than 20 in the Dragon Skin 10 Slow embodiment.
Kazeem teaches an average particle size of the liquid metal droplets that can be in the range of 1 to 200 microns [0028], but does not disclose the particle distribution, prompting one to look elsewhere in the art. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to modify the particle distribution of Kazem with the distribution of Kazem ‘218, a known suitable particle distribution for liquid metal droplets for applications in conductive composites, by providing a maximum particle size of about 48 or 20 microns as taught by Kazeem ‘218.
Accordingly, the D90 of the liquid metal droplets of Kazem in view of Kazem ‘218 prior to compressing the circuit assembly would be less than 20 or 48 microns, and the first layer thickness would be greater than 150 microns, thereby providing the first layer thickness of at least 1.1 times the D90 of the liquid metal droplets prior to compressing the circuit assembly.
Regarding claim 2, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the first layer thickness can be greater than 150 microns, and the times the D90 of the liquid metal droplets prior to compressing the circuit assembly is less than 20 microns (see rejection of claim 1), such that the first layer thickness is at least 2 times the D90 of the liquid metal droplets prior to compressing the circuit assembly.
Regarding claim 3, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the first layer thickness can be greater than 150 microns, and the times the D90 of the liquid metal droplets prior to compressing the circuit assembly is less than 20 microns (see rejection of claim 1), such that the first layer thickness is at least 4 times the D90 of the liquid metal droplets prior to compressing the circuit assembly.
Regarding claim 4, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the first layer thickness can be greater than 150 microns, and the times the D90 of the liquid metal droplets prior to compressing the circuit assembly is less than 20 microns (see rejection of claim 1), such that the first layer thickness is at least 5 times the D90 of the liquid metal droplets prior to compressing the circuit assembly.
Regarding claim 8, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the second layer thickness can be no greater than 150 microns (Kazem, [0043]).
Regarding claim 9, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the second layer thickness can be no greater than 120 microns (Kazem, [0043]).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
Regarding claim 10, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the second layer thickness is in a range of 15 microns to 150 microns (Kazem, [0043]).
Regarding claim 11, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the second layer thickness is in a range of 15 microns to 100 microns (Kazem, [0043]).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
Regarding claim 12 and 13, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the average particle size prior to compressing the circuit assembly is in a range of 1 to 200 microns (Kazem, [0028]).
Given that the average particle size ranges from 1 to 200 microns, D50 of the particles would also appear to be within the same range.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
Regarding claim 16, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the thermal interface material covers at least 90% of a surface area of an exposed side of the first layer after compressing the circuit assembly (Kazem, Figure 2A and 2B).
Regarding claim 17, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the depositing comprises at least one of dispensing, extruding, and/or applying with a utensil (Kazem, [0036]).
Regarding claim 18, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the compressing the circuit assembly comprises applying a first pressure to the first and second layer of at least 1 psi (Kazem, [0039], [0049]).
Regarding claim 19, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the compressing the circuit assembly comprises compressing based on displacement in order to reach the bondline thickness (Kazem, [0039]) and based on pressure in order to use low compression pressure (Kazem, [0044], [0049]). Therefore, the continuous compression applied of Kazem in view of Kazem ‘218 would include a first compression process and second compression process based on displacement and pressure.
Regarding claim 20, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the first layer and the second layer, individually, are at least one of a heat sink, an integrated heat spreader, and packaging (Kazem, [0004], [0035], [0060]).
Regarding claim 21, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the first layer comprises an integrated heat
spreader and the second layer comprises a heat sink (Kazem, [0035], [0047]).
Regarding claim 22, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the liquid metal droplets comprise at least one of gallium, a gallium alloy, indium, an indium alloy, tin, a tin alloy, mercury, and a mercury alloy (Kazem, [0025]).
Regarding claim 23, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the liquid metal droplets comprise a melting point no greater than 30 degrees Celsius (Kazem, [0025]).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
Regarding claim 24, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the thermal resistance value of no greater than 30 (°K*mm2)/W (Kazem, [0045]) and the thickness of the TIM is no greater than 150 microns (Kazem, [0043]).
Accordingly, the thermal interface material after compressing comprises an effective thermal conductivity value of at least 5 W/m*K [0045].
Regarding claim 25, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the thermal resistance value of no greater than 15 (°K*mm2)/W (Kazem, [0045]) and the thickness of the TIM is no greater than 150 microns (Kazem, [0043]).
Accordingly, the thermal interface material after compressing comprises an effective thermal conductivity value of at least 10 W/m*K [0045].
Regarding claim 26, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the thermal resistance value of no greater than 10 (°K *mm2)/W (Kazem, [0045]) and the thickness of the TIM is no greater than 150 microns (Kazem, [0043]).
Accordingly, the thermal interface material after compressing comprises an effective thermal conductivity value of at least 15 W/m*K [0045].
Regarding claim 27, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the polymer comprises a thermosetting polymer (Kazem, [0021], [0023]).
Regarding claim 28, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the polymer comprises a thermoplastic polymer (Kazem, [0021], [0024]).
Regarding claim 29, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the emulsion has a viscosity of less than 250,000 measured at room temperature (i.e., between 20 degrees Celsius and 25 degrees Celsius) (Kazem, [0026], [0034]).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
Regarding claim 30, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the liquid metal droplets are generally spherical prior to compressing and the liquid metal droplets are generally ellipsoidal after compressing the circuit assembly (Kazem, [0040], [0076]).
Regarding claim 31, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the liquid metal droplets comprise an aspect ratio of at least 2 after compressing the circuit assembly (Kazem, [0040]).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
Regarding claim 32, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein depositing comprises applying the thermal interface material direct to the first layer and, thereafter, directly applying the second layer to the thermal interface material (Kazem, [0036], [0046]).
Regarding claim 33, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein depositing comprises applying the thermal interface material direct to the second layer and, thereafter, directly applying the first layer to the thermal interface material (Kazem, [0036], [0046]).
Regarding claim 34, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein depositing comprises applying the thermal interface material to both the first layer and the second layer and then applying the first layer and the second layer together (Kazem, [0036]).
Regarding claim 35, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, further comprising curing the thermal interface material after compressing, thereby increasing the viscosity of the thermal interface material to maintain the second layer thickness (Kazem, [0032], [0034]).
Regarding claim 36, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, the thermal interface material comprises a contact angle suitable to efficiently wet at least one of a surface of the first layer and a surface of the second layer as supported by the fact that the thermal interface material is conformable to the surfaces of the die 206 and the upper layer 210 such that a desired level of surface contact therebetween can be achieved [0036], such that the material is deposited and spread onto the surface of the first layer and second layer and cured between the layers without deformity or voids (Kazem, Figures 2A, 2B, 3A, 3B).
Additionally, the thermal interface material of Kazem is identical to the claimed thermal interface material (e.g. identical material composition, particle composition, viscosity range, thermal resistivity range, curing temperature, etc.). Given that thermal interface material of Kazem is identical to the claimed thermal interface material, it appears that the contact angle of the thermal interface material of Kazem would also be identical to the claimed thermal interface material contact angle.
Claim 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kazem (PG-PUB 2021/0272873) in view of Kazem ‘218 (PG-PUB 2020/0362218), as applied to claim 1, in further view of Eid (PG-PUB 2021/0249375).
Regarding claim 5, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the first layer thickness can be greater than 150 microns, and the times the D90 of the liquid metal droplets prior to compressing the circuit assembly is less than 20 microns (see rejection of claim 1).
Kazem in view of Kazem ‘218 does not teach the first layer thickness is at least 10 times the D90 of the liquid metal droplets prior to compressing the circuit assembly.
Eid teaches a process of manufacturing an integrated circuit die structure comprising thermal interface material (Figures 1A-1C). Eid teaches the TIM is a layer of a thermal grease or paste having a thickness of 20 to 1000 microns between the hybrid
backside thermal structure on one side and an IHS on the other side, or between the hybrid backside thermal structure or IHS on one side and a system level cooling solution, such as a heat sink or cold plate coupled to a heat pipe or vapor
chamber, on the other side [0028].
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to modify the process of Kazem with the thermal interface layer thickness of Eid, a known suitable thermal interface layer for a composite, to yield the predictable result of providing an integrated circuit assembly.
Given that the second layer thickness of Kazem in view of Kazem ‘218 and Eid have a thickness of 1000 microns, the first layer of thickness would be greater than 1000 microns, thereby providing the first layer thickness is at least 10 times the D90 of the liquid metal droplets prior to compressing the circuit assembly.
Regarding claim 6 and 7, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein the first layer thickness can be greater than 150 microns, and the times the D90 of the liquid metal droplets prior to compressing the circuit assembly is less than 20 microns (see rejection of claim 1).
Kazem in view of Kazem ‘218 does not teach the first layer thickness is at least 200 microns.
Kazem in view of Kazem ‘218 does not teach the first layer thickness is at least 500 microns.
Eid teaches a process of manufacturing an integrated circuit die structure comprising thermal interface material (Figures 1A-1C). Eid teaches the TIM is a layer of a thermal grease or paste having a thickness of 20 to 1000 microns between the hybrid
backside thermal structure on one side and an IHS on the other side, or between the hybrid backside thermal structure or IHS on one side and a system level cooling solution, such as a heat sink or cold plate coupled to a heat pipe or vapor
chamber, on the other side [0028].
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to modify the process of Kazem with the thermal interface layer thickness of Eid, a known suitable thermal interface layer for a composite, to yield the predictable result of providing an integrated circuit assembly.
Given that the second layer thickness of Kazem in view of Kazem ‘218 and Eid have a thickness of 1000 microns, the first layer of thickness would be greater than 1000 microns.
Claim 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kazem (PG-PUB 2021/0272873) in view of Kazem ‘218 (PG-PUB 2020/0362218), as applied to claim 1, in further view of Yeh (PG-PUB 2019/0371700).
Regarding claim 14 and 15, Kazem in view of Kazem ‘218 teaches the process as applied to claim 1, wherein a single horizontal TIM layer can be in contact with multiple dies on one side (e.g., the integrated circuit can comprise multiple dies or multiple integrated circuits can be in contact with the same side of the TIM) and a upper layer or layers on a different side (Kazem, [0048]).
Kazem in view of Kazem ‘218 does not explicitly teach the depositing forms a trace extending along at least 10% of a length of the first layer and at least 1% of a width of the first layer.
Kazem in view of Kazem ‘218 does not explicitly teach the depositing forms a linear trace extending along a range of 50% to 90% of a length of the first layer and a range of 5% to 50% of a width of the first layer.
Yeh teaches a process of manufacturing a semiconductor package structure [0025]-[0032], comprising a multi-TIM structure disposed over plurality of semiconductor dies (Figure 2C and 3, items 120 and 122), a first TIM layer (Figure 2B, 2C, and 3, item 142 and [0029]) disposed in the first area, and a second TIM layer disposed in the second area (Figure 2B, 2C, and 3, item 144 and [0029]). Based on Figure 2C [0029]-[0030], it appears the deposited TIM 142 extends along (1) a range of 50% to 90% of a length of the first layer and a range of 5% to 50% of a width of the first layer and (2) along at least 10% of a length of the first layer and at least 1% of a width of the first layer.
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to modify the process of Kazem with the semiconductor package structure configuration of Yeh, a known suitable die structure configurations, to yield the predictable result of providing a semiconductor package structure using multiple dies as suggested by Kazem.
Conclusion
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/HANA C PAGE/Examiner, Art Unit 1745