Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/527,739 filed on March 12, 2026.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
5. Applicant’s election with traverse of claims 1-12, Group II, drawn to method claims, in the reply filed on 03/12/2026 is acknowledged.
6. Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected Group I, drawn device claims, there being no allowable generic or linking claim.
7. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/03/2025. The applicant states reason (s) on traversal that “failed to articulate facts sufficient to demonstrate….”. The office has realized that the applicant was unable to comprehend the cause of the restriction requirement, that there are two different inventions, device vs method, which has specifically mentioned in the restriction requirement. As said, the application contains different inventions wherein only one of the inventions is considered for examining per each application. Because the different inventions comprise different drawing structures/claims that impose burden to the examiner for creating different search strategies; searching various CPC symbols, non-patent languages (NPLs) and text searches that require extra amount of search time. Therefore, the remark with respect to the restriction requirement was not found not persuasive, and the restriction requirement is still deemed proper and is therefore made FINAL.
Specification
8. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Structure With Chipset Including Multiple Chips, and Memory”.
Claims Corrections
9. Claims 2, 6, 7 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or perform proper alignment along with the prior claim languages:
2. (Currently Amended) The method of forming a semiconductor structure of claim 1, wherein a plurality of chipsets are provided, and the plurality of chipsets are distributed at intervals; gaps between the plurality of chipsets are filled with the insulating dielectric layer; each of the plurality of chipsets comprises a bottom chip and a top chip; in a direction parallel to the carrier board, a first spacing exists between adjacent bottom chips, and a second spacing exists between adjacent top chips; and a width of the second spacing is less than a width of the first spacing.
6. (Currently Amended) The method of forming a semiconductor structure of claim 2, further comprising:
forming a logic chip between the plurality of chipsets and the carrier board, wherein an orthographic projection of the plurality of chipsets on the carrier board is within an orthographic projection of the logic chip on the carrier board.
7. (Currently Amended) The method of forming a semiconductor structure of claim 6, further comprising:
after the grinding process, performing a cutting process in the first spacing and the second spacing between the plurality of chipsets to separate the plurality of chipsets.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
12. Claims 1-3, 5-10, 12 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chen et al. (US 2021/0375827 A1).
Regarding independent claim 1, Chen et al. teaches a method of forming a semiconductor structure, comprising (Figs. 4C-4G):
providing a carrier board (100, para [0042]);
forming a chipset (102, 108) on one side of the carrier board (100), wherein the chipset (102, 108) comprises a plurality of chips (20a1…., para [0050]) stacked in a direction perpendicular to the carrier board (100); wherein among the plurality of chips (20a1….), an orthographic projection of a chip (20a1) closer to the carrier board (100) on the carrier board (100) is within an orthographic projection of a chip (108) farthest from the carrier board (100) on the carrier board (100);
forming an insulating dielectric layer (110’, para [0054, see Fig. 4D]) covering the chipset (102, 108); and
performing a grinding process (planarization process, see Fig. 4D-Fig. 4E, para [0056]) to expose a predetermined surface of the chip (108) farthest from the carrier board (100) outside the insulating dielectric layer (110).
Regarding claim 2, Chen et al. teaches wherein (Figs. 4C-4G), a plurality of chipsets (102, 108) are provided, and the plurality of chipsets (102, 108) are distributed at intervals; gaps between the plurality of chipsets (102, 108) are filled with the insulating dielectric layer (110’, see Fig. 4D); each of the plurality of chipsets (102,108) comprises a bottom chip (20a1) and a top chip (108); in a direction parallel to the carrier board (100), a first spacing (see the annotated figure below) exists between adjacent bottom chips (20a1 left, 20a1 right, see Fig. 4D), and a second spacing (see the annotated figure below) exists between adjacent top chips (108 left, 108 right); and a width (d2) of the second spacing is less than a width (d1) of the first spacing.
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Regarding claim 3, Chen et al. teaches wherein (Figs. 4C-4G), in the direction parallel to the carrier board (100), the bottom chip (20a1) has a first width (horizontal length, d11, see figure in claim 2), the top chip (108) has a second width (horizontal length, d22, see figure in claim 2), and the second width (d22) is greater (d22>d11) than the first width (d11).
Regarding claim 5, Chen et al. teaches wherein (Figs. 4C-4G), each of the plurality of chips (102, 108) comprises a substrate and a circuit module formed on a surface of the substrate; and in the top chip (108), a surface on which the circuit module is formed faces towards the carrier board (100).
Regarding claim 6, Chen et al. teaches wherein (Figs. 4C-4G), further comprising:
forming a logic chip (40a, see Fig. 4C) between the plurality of chipsets (102, 108) and the carrier board (100), wherein an orthographic projection of the plurality of chipsets (102, 108) on the carrier board (100) is within an orthographic projection of the logic chip (40a) on the carrier board (100).
Regarding claim 7, Chen et al. teaches wherein (Figs. 4C-4G), further comprising:
after the grinding process (see Fig. 4E), performing a cutting process (Fig. 4G) in the first spacing and the second spacing between the plurality of chipsets (102, 108) to separate the plurality of chipsets (102, 108).
Regarding claim 8, Chen et al. teaches wherein (Figs. 4C-4G), during the cutting process (sawing or laser cutting, para [0061], see Fig. 4F), the insulating dielectric layer (110’) is at least partially retained in the first spacing (see Fig. 4G).
Regarding claim 9, Chen et al. teaches wherein (Figs. 4C-4G), further comprising:
removing (see Fig. 4G, para [0059]) the carrier board (100: see Fig. 4F vs. Fig. 4G) after performing the cutting process, and electrically connecting a surface of the logic chip (40a) facing away from the chipset (20a1) to a substrate board (para [0122] coupled to a package component PC through the conductive terminals 150 which maybe a package substrate, see Fig. 14).
Regarding claim 10, Chen et al. teaches wherein (Figs. 4C-4G), further comprising:
forming a logic chip (40a, para [0048]) between the chipset (20a1) and the carrier board (100), wherein an orthographic projection of the chipset (20a1) on the carrier board (100) is within an orthographic projection of the logic chip (40a) on the carrier board (100).
Regarding claim 12, Chen et al. teaches wherein (Figs. 4C-4G), further comprising:
forming a logic chip (40a, para [0048]) between the chipset (20a1) and the carrier board (100), wherein an orthographic projection of the chipset (20a1) on the carrier board (100) is within an orthographic projection of the logic chip (40a) on the carrier board (100).
Allowable Subject Matter
13. Claim 4 (claim 11 depends on the claim 4) is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4: the prior art of record alone or in combination neither teaches nor makes obvious the method of forming the semiconductor structure, comprising:
Claim 4 recites ….performing the grinding process (planarization process) to expose the predetermined surface of the chip farthest from the carrier board outside the insulating dielectric layer comprises:
grinding to remove the insulating dielectric layer by a first target thickness, to expose a top surface of the top chip; and
grinding to remove the top chip and the insulating dielectric layer by a second target thickness, to expose the predetermined surface of the top chip, the second target thickness being not greater than the first target thickness.
The cited prior arts, Chen et al. (US 2021/0375827 A1) and/or w/ other prior art NAH (US 2018/0286835 A1) are close to the instant application, but do not explicitly disclose the process steps of grinding to remove the insulating dielectric layer by a first target thickness, to expose a top surface of the top chip; and grinding to remove the top chip and the insulating dielectric layer by a second target thickness.
Examiner’s Note
14. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
16. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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