DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 28 April 2026 of Applicants’ amendments of the drawings and specification and the amendments of the claims, in which claim 1, 3, and 4 are amended and claim 2 is cancelled. The Office withdraws the objection to the drawings identified in the Office Communication dated 2 February 2026 in view of the amendments.
Response to Arguments
Applicants’ arguments with respect to independent claim(s) 1 have been considered but are not persuasive. Specifically, Applicants argue in the second and third paragraphs of page 9 that Lee does not teach the subject matter newly added to claim 1 whereby “a first thickness of the first portion [of the redistribution portion] located on the first surface [of the first encapsulation layer] is greater than a second thickness of the first portion located on the second surface [of the first encapsulation layer].” Claim 1 is rejected as being anticipated by Lee. A claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference. MPEP §2131. As this principle applies to the present circumstance, Lee teaches in Fig. 1 a first thickness (vertical thickness) of the first portion (of 131) located on the first surface (bottom surface of 120) is greater than a second thickness (vertical thickness) of the first portion (of 131) located on the second surface (top surface of 120) {see, e.g., the alternative annotated copies of Lee’s Fig. 1 and Examiner’s Note, below}.
Examiner’s Note: The American Heritage College Dictionary, 4th edition, defines “on” as: (1) [u]sed to indicate position above and supported by or in contact with or (2) [u]sed to indicate contact with or extent over.
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With the exception discussed immediately below, Applicants’ arguments with respect to independent claim(s) 3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants argue in the second paragraph of page 11 and with respect to claim 3 that Lee does not teach “a seed + plating layer for each of the first and second conductive layers.” Claim 1 is rejected over the combined teachings of Lee and Costa and recites “the first conductive layer includes a first seed layer and a first plating layer … [and] the second conductive layer includes a second seed layer and a second plating layer.” Arguments presented by applicant cannot take the place of evidence in the record. MPEP 2145(I); as this principle applies to the present circumstance Lee teaches in paragraph [0073] a redistribution pattern 131 may be formed by a seed layer forming process … and an electro-plating process. Accordingly, Lee teaches in Fig. 1 the first conductive layer (portion of 131 extending horizontally above 120 and penetrating 240) includes a first seed layer and a first plating layer and the second conductive layer (portion of 131 extending horizontally below 120 and penetrating 140) includes a second seed layer and a second plating layer.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4, lines 3 and 4, recites “the first encapsulation layer includes a first surface and a second surface opposite to each other, and a through hole passing through the first surface and the second surface,” which is indefinite because: (A) this recitation is identical to that in lines 1-12 of base claim 1 and (B) it is unclear whether the recited: (1) “a first surface,” (2) “a second surface,” and (3) “a through hole” are the same as those recited in lines 10-12 of base claim 1. For the purpose of compact prosecution and to better comport with base claim 1, the entirety of this repeated and identical recitation (including the: (1) word “wherein” preceding and (2) conjunctive feature of “, and” following the recitation) will be omitted from dependent claim 4.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 4-8 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee (US20190229101A1).
Regarding claim 1, Lee teaches in Fig. 1/7 a semiconductor package comprising:
a first package (100/310) including a first semiconductor chip (110/311), a first encapsulation layer (120/312) covering a side surface of the first semiconductor chip (110/311), and a first redistribution pattern (130/313) connected to a pad (110p/{pad of 311}) of the first semiconductor chip (110/311) {[0052, 0056]/[0105, 0108]}; and
a second package (200/320) provided on the first package (100/310) and including a second semiconductor chip (210/321), a second encapsulation layer (220/322) covering the second semiconductor chip (210/321), and a second redistribution pattern (230/323) connected to a pad (210p/{pad of 321}) of the second semiconductor chip (210/321) {[0062, 0064]/[0105, 0108]},
wherein the first redistribution pattern (130/313) is connected to the second redistribution pattern (230/323) through the first encapsulation layer (120/312) {[0056]/[0108]; ¶0105 and 0110 teach that Fig. 7 may have features similar to those of Fig. 1},
wherein the first encapsulation layer (120) includes a first surface (bottom surface of 120) and a second surface (top surface of 120) opposite to each other, and a through hole (120H) passing through the first surface (bottom surface of 120) and the second surface (top surface of 120) {[0054]},
wherein the first redistribution pattern (130) includes a first portion (vertical portion of 130 within and above 120H) extending from the first surface (bottom surface of 120) to the second surface (top surface of 120) through the through hole (120H) and a second portion (portion of 130 extending horizontally above 120 and penetrating 240) connected to the first portion (vertical portion of 130 within and above 120H) and extending on (e.g., above) the first surface (bottom surface of 120) {Fig. 1; the second portion may be a part of the first portion}, and
wherein a first thickness (vertical thickness) of the first portion (vertical portion of 130 within and above 120H) located on (e.g., above) the first surface (bottom surface of 120) is greater than a second thickness (vertical thickness) of the first portion (vertical portion of 130 within and above 120H) located on (e.g., above) the second surface (top surface of 120) {i.e., the vertical portion of 130 above 120H and above the top surface of 120 has a smaller vertical thickness than does the vertical portion of 130 within and above 120H} {see, e.g., the alternative annotated copies of Lee’s Fig. 1, below}.
Examiner’s Note: The American Heritage College Dictionary, 4th edition, defines “on” as: (1) [u]sed to indicate position above and supported by or in contact with or (2) [u]sed to indicate contact with or extent over.
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Regarding claim 4, as interpreted in view of the indefiniteness rejection, Lee teaches in Fig. 1 the semiconductor package of claim 1, and Lee further teaches
wherein the first redistribution pattern (130) is connected to the pad (210p) of the second semiconductor chip (210) by being directly connected to the second redistribution pattern (230) through the through hole (120H) {[0056]}.
Regarding claim 5, Lee teaches in Fig. 7 the semiconductor package of claim 1, and Lee further teaches further comprising an electromagnetic wave shielding layer (350) covering at least a portion of the first package (310) and at least a portion of the second package (320) {[0111]}.
Regarding claim 6, Lee teaches in Fig. 7 the semiconductor package of claim 5, and Lee further teaches further comprising an outer encapsulation layer (360) covering the first package (310), the second package (320), and the electromagnetic wave shielding layer (350) {[0113]}.
Regarding claim 7, Lee teaches in Fig. 7 the semiconductor package of claim 6, and Lee further teaches further comprising a lower conductive layer (370) extending on the first package (310) and the outer encapsulation layer (360) {[0115]},
wherein the lower conductive layer (370) is electrically connected to the first redistribution pattern (313) of the first package (310) and the electromagnetic wave shielding layer (350) {[0116, 0117]}.
Regarding claim 8, Lee teaches in Fig. 7 the semiconductor package of claim 7, and Lee further teaches further comprising a thermal conductive film (380) provided on the first package (310) and the outer encapsulation layer (360) and covering at least a portion of the lower conductive layer (370) {[0114, 0119]}.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Costa et al. (US20240030117A1).
Regarding claim 3, Lee teaches in Fig. 1 a semiconductor package comprising:
a first package (100/310) including a first semiconductor chip (110/311), a first encapsulation layer (120/312) covering a side surface of the first semiconductor chip (110/311), and a first redistribution pattern (131/313) connected to a pad (110p/{pad of 311}) of the first semiconductor chip (110/311) {[0052, 0056]/[0105, 0108]}; and
a second package (200/320) provided on the first package (100/310) and including a second semiconductor chip (210/321), a second encapsulation layer (220/322) covering the second semiconductor chip (210/321), and a second redistribution pattern (230/323) connected to a pad (210p/{pad of 321}) of the second semiconductor chip (210/321) {[0062, 0064]/[0105, 0108]},
wherein the first redistribution pattern (131/313) is connected to the second redistribution pattern (230/323) through the first encapsulation layer (120/312) {[0056]/[0108]; ¶0105 and 0110 teach that Fig. 7 may have features similar to those of Fig. 1},
wherein the first encapsulation layer (120) includes a first surface (bottom surface of 120) and a second surface (top surface of 120) opposite to each other, and a through hole (120H) passing through the first surface (bottom surface of 120) and the second surface (top surface of 120) {[0054]},
wherein the first redistribution pattern (131) includes a first conductive layer (portion of 131 extending horizontally above 120 and penetrating 240) disposed on an inner surface of the through hole (120H) and connected to the second package (200), and a second conductive layer (portion of 131 extending horizontally below 120 and penetrating 140) disposed on the first surface (bottom surface of 120) and connected to the first conductive layer (portion of 131 extending horizontally above 120 and penetrating 240) and the pad (110p) of the first semiconductor chip (110) {Fig. 1},
wherein the first conductive layer (portion of 131 extending horizontally above 120 and penetrating 240) includes a first seed layer and a first plating layer that are sequentially disposed on the inner surface of the through hole (120H) {[0073], redistribution pattern 131 may be formed by a seed layer forming process … and an electro-plating process},
wherein the second conductive layer (portion of 131 extending horizontally below 120 and penetrating 140) includes a second seed layer and a second plating layer that are sequentially disposed on the first surface (bottom surface of 120) of the first encapsulation layer (120) {[0073], redistribution pattern 131 may be formed by a seed layer forming process … and an electro-plating process}.
Lee does not teach expressly that the first plating layer is formed to be thicker than the first seed layer, and the second plating layer is formed to be thicker than the second seed layer.
In an analogous art, Costa teaches in Fig. 16 and paragraph [0080] a plating layer (88) is formed to be thicker than a seed layer (86). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s semiconductor package based on the teachings of Costa – such that Lee’s first plating layer is formed to be thicker than Lee’s first seed layer, and Lee’s second plating layer is formed to be thicker than Lee’s second seed layer – because , all the claimed elements (e.g., seed layer, plating layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Costa) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: The American Heritage College Dictionary, 4th edition, defines “on” to mean: (1) [u]sed to indicate position above and supported by or in contact with or (2) [u]sed to indicate contact with or extent over.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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