DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/04/2023 was filed after the mailing date of the application on 12/04/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I and the corresponding claims 1-17 in the reply filed on 02/11/2026 is acknowledged.
Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/11/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20230093897 A1 (Kim) in view of Wu et al, US 20210202323 A1 (Wu) in further view of Zhang et al, US 10763177 B1 (Zhang).
Regarding claim 1; Kim teaches a semiconductor structure (100), comprising: a first nanosheet field-effect transistor device comprising a plurality of first nanosheet channel layers (135) and a first interfacial layer (154-1) surrounding each of the plurality of first nanosheet channel layers (135), the first interfacial layer having a first thickness (see Fig (4) of Kim); and a second nanosheet field-effect transistor device vertically stacked above the first field-effect transistor nanosheet device (see Figures (3) and (4) of Kim), the second field-effect transistor nanosheet device comprising a plurality of second nanosheet channel layers (135) and a second interfacial layer (154-1) surrounding each of the plurality of second nanosheet channel layers (135).
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Kim does not teach the second interfacial layer having a second thickness greater than the first thickness. However, Wu teaches the second interfacial layer (252c) having a second thickness (TIL3) greater than the first thickness (TIL2) (see paragraph [0034] of the specification of Wu: [0034]… After operation 120, a thickness TIL2 of the interfacial layer 252b is larger than a thickness TIL2 of the interfacial layer 252a, but still smaller than a thickness TIL3 of the interfacial layer 252c”). Kim and Wu are considered analogous art. Thus, it would have been obvious prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by making the thickness of the second interfacial layer greater than the first thickness of the interfacial layer between the nanosheets as disclosed in Wu to improve the insulation between the nanosheet channel layers leading to a better performing device.
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Kim in view of Wu does not teach wherein a distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.
Zhang teaches wherein a distance between each of the plurality of second nanosheet channel layers ((108a’), (108b’) and (108c’)) is less than a distance between each of the plurality of first nanosheet channel layers ((108a’’), (108b’’) and (108c’’)) (see annotated Fig (15) of Zhang shared in this OA for a comparison between D-1representing the distance between the first nanosheet channel layers and D-2 representing the distance between the second nanosheet channel layers).
Kim in view of Wu and Zhang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim in view of Wu by making the distance between the second set of nanosheet channel layers to allow for increasing the density of channel layers which leads to more simultaneous transistor operations utilizing the same area of the device which leads to a faster performing device.
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Regarding claim 3; Kim teaches wherein the first interfacial layers (154-1) and the second interfacial layers (154-1) comprise the same interfacial material (see paragraphs [0057] – [0060] of the specification of Kim.
Regarding claim 4; Kim in view of Wu does not teach wherein the first interfacial layers have a thickness of about 0.1 to about 0.5 nm and the second interfacial layers have a thickness of about 0.5 to about 1.0 nm.
Zhang teaches wherein the first interfacial layers (902) have a thickness of about 0.1 to about 0.5 nm and the second interfacial layers (906) have a thickness of about 0.5 to about 1.0 nm (see Col.: 7 Row.: 17-20 of the specification of Zhang: According to an exemplary embodiment, IL oxide 902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm). While Zhang’s first embodiment discussed in the rejections above did not specify these limitations of the interfacial layers (902/906) which are discussed in this embodiment, the two embodiments are considered analogous art and they appear to share these limitations given the existence of the interfacial layers (902/906) in the first embodiment in absence of further discussion from Zhang regarding any changes in its thickness. Kim in view of Wu and Zhang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim in view of Wu and Zhang’s first embodiment by making the thicknesses of the first and second interfacial layers in the ranges disclosed by Zhang’s second embodiment to improve the insulation of the nanosheet channels while increasing the density of the components in the device leading to a better performing device that is more reliable.
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Regarding claim 5; Kim does not teach further comprising a dielectric layer surrounding each of the first interfacial layers and the second interfacial layers.
Wu teaches further comprising a dielectric layer ((254b) and (254c)) surrounding each of the first interfacial layers (252b) and the second interfacial layers (252c).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by constructing a dielectric layer surrounding the first and second interfacial layers as disclosed in Wu to improve the insulation of the nanosheet channel layers leading to a more reliable device.
Regarding claim 6; Kim does not teach wherein the dielectric layer comprises a high-k dielectric material with a k-value greater than 3.9.
Wu teaches wherein the dielectric layer comprises a high-k dielectric material with a k-value greater than 3.9 (see paragraph [0032] of the specification of Wu).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by constructing a dielectric layer surrounding the first and second interfacial layers that have a dielectric constant greater than 3.9 as disclosed in Wu to improve the insulation of the nanosheet channel layers leading to a more reliable device.
Regarding claim 7; Kim does not teach further comprising a work function metal disposed on the dielectric layer surrounding each of the first interfacial layers and the second interfacial layers.
Wu teaches further comprising a work function metal (282) disposed on the dielectric layer ((254b) and (254c)) surrounding each of the first interfacial layers (252b) and the second interfacial layers (252c) (see paragraph [0039] of the specifications of Wu: “[0039]… The gate electrode layer 282 is a conductive layer that includes one or more metal layers, such as work function metal layer(s), conductive barrier layer(s), and metal fill layer(s). The gate electrode layer 282 may be formed separately for n-type and p-type transistors which may use different metal layers. The work function metal layer may be a p-type or an n-type work function layer.”).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by using a work function metal disposed on the dielectric layers as disclosed in Wu to improve the electrical performance of the transistor leading to a better perming device.
Regarding claim 8; Kim does not teach wherein the work function metal is a p-type work function metal.
Wu teaches wherein the work function metal (282) is a p-type work function metal (see paragraph [0039] of the specifications of Wu: “[0039]… The gate electrode layer 282 is a conductive layer that includes one or more metal layers, such as work function metal layer(s), conductive barrier layer(s), and metal fill layer(s). The gate electrode layer 282 may be formed separately for n-type and p-type transistors which may use different metal layers. The work function metal layer may be a p-type or an n-type work function layer.”).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by using a p-type work function metal as disclosed in Wu to enhance the performance of the transistors and thus improve the performance of the device.
Regarding claim 9; Kim does not teach further comprising a gate fill metal disposed over the work function metal.
Wu teaches further comprising a gate fill metal disposed over the work function metal (282) (see paragraph [0039] of the specifications of Wu: “[0039]… The gate electrode layer 282 is a conductive layer that includes one or more metal layers, such as work function metal layer(s), conductive barrier layer(s), and metal fill layer(s). The gate electrode layer 282 may be formed separately for n-type and p-type transistors which may use different metal layers. The work function metal layer may be a p-type or an n-type work function layer.”).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by using a gate fill metal disposed over the work function metal as disclosed in Wu to improve electrostatic charges control in the transistor leading to a better performing device.
Regarding claim 10; Kim teaches wherein the first nanosheet field-effect transistor (135) device is of a first polarity and the second nanosheet field-effect transistor (135) device is of a second polarity different than the first polarity (see paragraphs [0045] and [0088] of the specification of Kim).
Regarding claim 11; Kim teaches a semiconductor structure, comprising: an N-type (see paragraphs [0045] and [0088] of the specifications of Kim) nanosheet field-effect transistor (135) device comprising a plurality of first nanosheet channel layers (135) having a first length (W2) and a first interfacial layer (154-1) surrounding each of the plurality of first nanosheet channel layers (135), the first interfacial layer having a first thickness (see Figure (4) of Kim); and a P-type (see paragraphs [0045] and [0088] of the specifications of Kim) nanosheet field-effect transistor device vertically stacked above the N-type nanosheet field-effect transistor device (see paragraphs [0045] and [0088] of the specifications of Kim), the P-type nanosheet field-effect transistor (135) device comprising a plurality of second nanosheet channel layers (135) having a second length (W2) and a second interfacial layer (154-1) surrounding each of the plurality of second nanosheet channel layers (135).
Kim does not teach the second interfacial layer having a second thickness greater than the first thickness. However, Wu teaches the second interfacial layer (252c) having a second thickness (TIL3) greater than the first thickness (TIL2) (see paragraph [0034] of the specification of Wu: [0034]… After operation 120, a thickness TIL2 of the interfacial layer 252b is larger than a thickness TIL2 of the interfacial layer 252a, but still smaller than a thickness TIL3 of the interfacial layer 252c”). Kim and Wu are considered analogous art. Thus, it would have been obvious prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by making the thickness of the second interfacial layer greater than the first thickness of the interfacial layer between the nanosheets as disclosed in Wu to improve the insulation between the nanosheet channel layers leading to a better performing device.
Kim in view of Wu does not teach wherein a distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.
Zhang teaches wherein a distance between each of the plurality of second nanosheet channel layers ((108a’), (108b’) and (108c’)) is less than a distance between each of the plurality of first nanosheet channel layers ((108a’’), (108b’’) and (108c’’)) (see annotated Fig (15) of Zhang shared in this OA for a comparison between D-1representing the distance between the first nanosheet channel layers and D-2 representing the distance between the second nanosheet channel layers)..
Kim in view of Wu and Zhang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim in view of Wu by making the distance between the second set of nanosheet channel layers to allow for increasing the density of channel layers which leads to more simultaneous transistor operations utilizing the same area of the device which leads to a faster performing device.
Regarding claim 13; Kim teaches wherein the first interfacial layers (154-1) and the second interfacial layers (154-1) comprise the same interfacial material (see paragraphs [0057] – [0060] of the specification of Kim.
Regarding claim 14; Kim does not teach further comprising a dielectric layer surrounding each of the first interfacial layers and the second interfacial layers.
Wu teaches further comprising a dielectric layer ((254b) and (254c)) surrounding each of the first interfacial layers (252b) and the second interfacial layers (252c).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by constructing a dielectric layer surrounding the first and second interfacial layers as disclosed in Wu to improve the insulation of the nanosheet channel layers leading to a more reliable device.
Regarding claim 15; Kim does not teach wherein the dielectric layer comprises a high-k dielectric material with a k-value greater than 3.9.
Wu teaches wherein the dielectric layer comprises a high-k dielectric material with a k-value greater than 3.9 (see paragraph [0032] of the specification of Wu).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by constructing a dielectric layer surrounding the first and second interfacial layers that have a dielectric constant greater than 3.9 as disclosed in Wu to improve the insulation of the nanosheet channel layers leading to a more reliable device.
Regarding claim 16; Kim does not teach further comprising a work function metal disposed on the dielectric layer surrounding each of the first interfacial layers and the second interfacial layers.
Wu teaches further comprising a work function metal (282) disposed on the dielectric layer ((254b) and (254c)) surrounding each of the first interfacial layers (252b) and the second interfacial layers (252c) (see paragraph [0039] of the specifications of Wu: “[0039]… The gate electrode layer 282 is a conductive layer that includes one or more metal layers, such as work function metal layer(s), conductive barrier layer(s), and metal fill layer(s). The gate electrode layer 282 may be formed separately for n-type and p-type transistors which may use different metal layers. The work function metal layer may be a p-type or an n-type work function layer.”).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by using a work function metal disposed on the dielectric layers as disclosed in Wu to improve the electrical performance of the transistor leading to a better perming device.
Regarding claim 17; Kim does not teach wherein the work function metal is a p-type work function metal.
Wu teaches wherein the work function metal (282) is a p-type work function metal (see paragraph [0039] of the specifications of Wu: “[0039]… The gate electrode layer 282 is a conductive layer that includes one or more metal layers, such as work function metal layer(s), conductive barrier layer(s), and metal fill layer(s). The gate electrode layer 282 may be formed separately for n-type and p-type transistors which may use different metal layers. The work function metal layer may be a p-type or an n-type work function layer.”).
Kim and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by using a p-type work function metal as disclosed in Wu to enhance the performance of the transistors and thus improve the performance of the device.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20230093897 A1 (Kim) in view of Wu et al, US 20210202323 A1 (Wu) in further view of Zhang et al, US 10763177 B1 (Zhang) in further view of M. G. Bardon et al., "Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells," 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 2018, pp. 143-144, doi: 10.1109/VLSIT.2018.8510633, (Bardon).
Regarding claim 2; Kim in view of Wu in further view of Zhang does not teach wherein the distance between each of the plurality of second nanosheet channel layers is from about 1 to about 3 nanometers (nm) less than the distance between each of the plurality of first nanosheet channel layers.
Bardon teaches wherein the distance between each of the plurality of second nanosheet channel layers (NanoSheet – see Figure (1) of Bardon shared in this OA) is from about 1 to about 3 nanometers (nm) less than the distance between each of the plurality of first nanosheet channel layers (see Figure (1) and the Conclusion section of Bardon).
Kim in view of Wu in further view of Zhang and Bardon are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim in view of Wu in further view of Zhang by making the difference in the spacing between the second set of nanosheet channel layers and the first set of the nanosheet channel layers between 1 nm and 3 nm to retain the insulation between the different channel layers leading to a more reliable device.
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Regarding claim 12; Kim in view of Wu in further view of Zhang does not teach wherein the distance between each of the plurality of second nanosheet channel layers is from about 1 to about 3 nanometers (nm) less than the distance between each of the plurality of first nanosheet channel layers.
Bardon teaches wherein the distance between each of the plurality of second nanosheet channel layers (NanoSheet – see Figure (1) of Bardon shared in this OA) is from about 1 to about 3 nanometers (nm) less than the distance between each of the plurality of first nanosheet channel layers (see Figure (1) and the Conclusion section of Bardon).
Kim in view of Wu in further view of Zhang and Bardon are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim in view of Wu in further view of Zhang by making the difference in the spacing between the second set of nanosheet channel layers and the first set of the nanosheet channel layers between 1 nm and 3 nm to retain the insulation between the different channel layers leading to a more reliable device.
Conclusion
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/M.K./Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815