DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/21/2026 has been entered.
Remarks
The 07/21/2026 amendments of claims 1 and 11 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks page 5, filed 07/21/2026, with respect to the rejection of claims 1 and 11 (and their dependent claims 2-10 and 12-17) under 35 U.S.C. 112(a)(1) have been fully considered and are persuasive in light of the newly added amendments. The rejections of record have been withdrawn.
Applicant’s arguments, see Arguments pages 5-8, filed 07/21/2026, with respect to the rejection(s) of claim(s) 1-17 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Jo et al, US 20230352529 A1 (Jo).
New Grounds of Rejection
New grounds of rejection, prior art reference Jo et al, US 20230352529 A1 (Jo) appears below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al, US 20230352529 A1 (Jo) in view of Wu et al, US 20210202323 A1 (Wu) in further view of Zhang et al, US 10763177 B1 (Zhang).
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Regarding claim 1; Jo teaches a semiconductor structure (Jo: Annotated Fig (1C) shared in this OA: 10), comprising:
a first nanosheet field-effect transistor device (First Nanosheet Transistor Device) comprising a plurality of first nanosheet channel layers (110) having a first length (First Length) and a first interfacial layer (115D, [0047] The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer) surrounding each of the plurality of first nanosheet channel (110) layers,
the first interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) having a first thickness (First Thickness);
a second nanosheet field-effect transistor device (Second Nanosheet Transistor Device) vertically stacked above the first field- effect transistor nanosheet device (First Nanosheet Transistor Device), the second field-effect transistor nanosheet device (Second Nanosheet Transistor Device) comprising a plurality of second nanosheet channel layers (120C) having a second length (Second Length) less than the first length (First Length) and a second interfacial layer (115D) surrounding each of the plurality of second nanosheet channel layers (120C),
the second interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) having a second thickness (Second Thickness) greater than the first thickness; and
a middle dielectric insulation layer (130) disposed between the first nanosheet field-effect transistor device (First Nanosheet Transistor Device) and the second nanosheet field-effect transistor device (Second Nanosheet Transistor Device), wherein the second interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) is disposed on exterior surfaces of the middle dielectric insulation layer (130);
wherein a distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.
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Jo does not teach the second interfacial layer having a second thickness greater than the first thickness.
Wu teaches the second interfacial layer (Wu: Fig(13): 252c) having a second thickness (TIL3) greater than the first thickness (TIL2; [0034]).
Jo and Wu are considered analogous art. Thus, it would have been obvious prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jo by making the thickness of the second interfacial layer greater than the first thickness of the interfacial layer between the nanosheets as disclosed in Wu to improve the insulation between the nanosheet channel layers leading to a better performing device.
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While Jo in view of Wu teaches stacked nanosheet field-effect transistors and the structure of their channel sheets, it fails to disclose the comparative distances between the nanosheets. Thus, Jo in view of Wu fails to teach wherein a distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.
Zhang teaches wherein a distance (Zhang: Annotated Fig (15) shared in this OA:D-2) between each of the plurality of second nanosheet channel layers ((108a’); (108b’); (108c’)) is less than a distance (D-1) between each of the plurality of first nanosheet channel layers ((108a’’); (108b’’); (108c’’)).
Jo in view of Wu and Zhang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jo in view of Wu by making the distance between the second set of nanosheet channel layers smaller than those between the first nanosheet channels to allow for increasing the density of channel layers which leads to more simultaneous transistor operations utilizing the same area of the device which leads to a faster performing device.
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Regarding claim 3; Jo in view Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 1.
Further, Jo teaches wherein the first interfacial layer (Jo: Annotated Fig (1C) shared in this OA: 115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) and the second interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) comprise the same interfacial material ([0044] – [0047]).
Regarding claim 4; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 1.
However, Jo in view of Wu does not teach wherein the first interfacial layer has a thickness of about 0.1 to about 0.5 nm and the second interfacial layer has a thickness of about 0.5 to about 1.0 nm.
Zhang teaches wherein the first interfacial layer (Zhang: Fig (9): 902) has a thickness of about 0.1 to about 0.5 nm and the second interfacial layer (906) has a thickness of about 0.5 to about 1.0 nm (Col.: 7 Row.: 17-20).
While Zhang’s first embodiment discussed in the rejections above did not specify these limitations of the interfacial layers (902/906) which are discussed in this embodiment, the two embodiments are considered analogous art and they appear to share these limitations given the existence of the interfacial layers (902/906) in the first embodiment in absence of further discussion from Zhang regarding any changes in its thickness.
Jo in view of Wu and Zhang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jo in view of Wu and Zhang’s first embodiment by making the thicknesses of the first and second interfacial layers in the ranges disclosed by Zhang’s second embodiment to improve the insulation of the nanosheet channels while increasing the density of the components in the device leading to a better performing device that is more reliable.
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Regarding claim 5; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 1.
Jo teaches further comprising a dielectric layer (Jo: Annotated Fig (1C) shared in this OA: 115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) surrounding each of the first interfacial layers (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) and the second interfacial layers (115D: [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”).
Regarding claim 6; Jo in view of Wu in further view of Zhang teach all the limitations of the semiconductor structure according to claim 5.
Further, Jo teaches wherein the dielectric layer (Jo: Annotated Fig (1C) shared in this OA: 115D, [0047] The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer) comprises a high-k dielectric material with a k-value greater than 3.9 ([0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer formed of hafnium oxide, hafnium silicate, hafnium oxynitride…”).
Regarding claim 7; Jo in view of Wu in further view Zhang teaches all the limitations of the semiconductor structure according to claim 5.
Jo teaches further comprising a work function metal (Jo: Annotated Fig (1C) shared in this OA: 125F) disposed on the dielectric layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) surrounding each of the first interfacial layers (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) and the second interfacial layers (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”).
Regarding claim 8; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 7.
Jo teaches wherein the work function metal (Jo: Annotated Fig (1C) shared in this OA: 125F) is a p-type work function metal ([0051]: “The lower work-function metal layer 115F and the upper work-function metal layer 125F may each be formed of titanium (Ti), tantalum (Ta) or their compound such as TiN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, not being limited thereto.”).
Regarding claim 9; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 7.
Jo teaches further comprising a gate fill metal (Jo: Annotated Fig (1C) shared in this OA: 115E) disposed over the work function metal (125F).
Regarding claim 10; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 1.
Further, Jo teaches wherein the first nanosheet field-effect transistor (Jo: Annotated Fig (1C) shared in this OA: First Nanosheet Transistor Device) device is of a first polarity and the second nanosheet field-effect transistor (Second Nanosheet Transistor Device) device is of a second polarity different than the first polarity ([0048]: “On the gate dielectric layer 115D, the lower work-function metal layer 115F and the upper work-function metal layer 125F are formed to define polarity types of the lower nanosheet transistor 10L and the upper nanosheet transistor 10U between p-type and n-type and/or control respective gate threshold voltages for the two nanosheet transistors 10L and 10U.”)
Regarding claim 11; Jo teaches A semiconductor structure, comprising:
an N-type nanosheet field-effect transistor device (Jo: Annotated Fig (1C) shared in this OA: First Nanosheet Transistor Device, [0038]: “The lower source/drain regions 112 and the upper source/drain regions 122 may be doped with p-type or n-type dopants, depending on the type of field-effect transistor (FET) to be formed by the lower source/drain regions 112 and upper source/drain regions 112 and 122, respectively. For example, the lower source/drain regions 112 may be doped with or implanted by p-type dopants such as boron (B), gallium (Ga), etc. to form the lower nanosheet transistor 10L as a p-type FET (PFET), and the upper source/drain regions 122 may be doped with or implanted by n-type dopants such as phosphorous (As), arsenic (Sb), indium (In), etc. to form the upper nanosheet transistor 10U as an n-type FET (NFET). However, the embodiments are not limited thereto.”, and while the application mentions the example of the lower set of nanosheets being P-type, it explicitly mentions that the design can be altered to accommodate the opposite design depending on the polarity of the bottom device nanosheets and thus the current example is just an example among many) comprising a plurality of first nanosheet channel layers (110C) having a first length (First Length) and a first interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) surrounding each of the plurality of first nanosheet channel layers (110C), the first interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) having a first thickness (First Thickness);
a P-type nanosheet field-effect transistor device (Second Nanosheet Transistor Device, [0038], while the application mentions the example of the upper set of nanosheets being N-type, it explicitly mentions that the design can be altered to accommodate the opposite design depending on the polarity of the bottom device nanosheets and thus the current example is just an example among many) vertically stacked above the N-type nanosheet field-effect transistor device (First Nanosheet Transistor Device), the P-type nanosheet field-effect transistor device (Second Nanosheet Transistor Device) comprising a plurality of second nanosheet channel layers (120C) having a second length (Second Length) less than the first length (First Length) and a second interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) surrounding each of the plurality of second nanosheet channel layers (120C), the second interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) having a second thickness (Second Thickness) greater than the first thickness; and
a middle dielectric insulation layer (130) disposed between the N-type nanosheet field-effect transistor device (First Nanosheet Transistor Device) and the P-type nanosheet field-effect transistor device (Second Nanosheet Transistor Device), wherein the second interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) is disposed on exterior surfaces of the middle dielectric insulation layer (130);
wherein a distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.
Jo does not teach the second interfacial layer having a second thickness greater than the first thickness.
Wu teaches the second interfacial layer (Wu: Fig(13): 252c) having a second thickness (TIL3) greater than the first thickness (TIL2; [0034]).
Jo and Wu are considered analogous art. Thus, it would have been obvious prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jo by making the thickness of the second interfacial layer greater than the first thickness of the interfacial layer between the nanosheets as disclosed in Wu to improve the insulation between the nanosheet channel layers leading to a better performing device.
While Jo in view of Wu teaches stacked nanosheet field-effect transistors and the structure of their channel sheets, it fails to disclose the comparative distances between the nanosheets. Thus, Jo in view of Wu fails to teach wherein a distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.
Zhang teaches wherein a distance (Zhang: Annotated Fig (15) shared in this OA:D-2) between each of the plurality of second nanosheet channel layers ((108a’); (108b’); (108c’)) is less than a distance (D-1) between each of the plurality of first nanosheet channel layers ((108a’’); (108b’’); (108c’’)).
Jo in view of Wu and Zhang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jo in view of Wu by making the distance between the second set of nanosheet channel layers smaller than those between the first nanosheet channels to allow for increasing the density of channel layers which leads to more simultaneous transistor operations utilizing the same area of the device which leads to a faster performing device.
Regarding claim 13; Jo in view Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 11.
Further, Jo teaches wherein the first interfacial layer (Jo: Annotated Fig (1C) shared in this OA: 115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) and the second interfacial layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) comprise the same interfacial material ([0044] – [0047]).
Regarding claim 14; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 11.
Jo teaches further comprising a dielectric layer (Jo: Annotated Fig (1C) shared in this OA: 115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) surrounding each of the first interfacial layers (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) and the second interfacial layers (115D: [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”).
Regarding claim 15; Jo in view of Wu in further view of Zhang teach all the limitations of the semiconductor structure according to claim 14.
Further, Jo teaches wherein the dielectric layer (Jo: Annotated Fig (1C) shared in this OA: 115D, [0047] The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer) comprises a high-k dielectric material with a k-value greater than 3.9 ([0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer formed of hafnium oxide, hafnium silicate, hafnium oxynitride…”).
Regarding claim 16; Jo in view of Wu in further view Zhang teaches all the limitations of the semiconductor structure according to claim 14.
Jo teaches further comprising a work function metal (Jo: Annotated Fig (1C) shared in this OA: 125F) disposed on the dielectric layer (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) surrounding each of the first interfacial layers (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”) and the second interfacial layers (115D, [0047]: “The gate dielectric layer 115D may include an interfacial layer formed of silicon oxide and/or silicon oxynitride, not being limited thereto, and a high-k layer…”).
Regarding claim 17; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 16.
Jo teaches wherein the work function metal (Jo: Annotated Fig (1C) shared in this OA: 125F) is a p-type work function metal ([0051]: “The lower work-function metal layer 115F and the upper work-function metal layer 125F may each be formed of titanium (Ti), tantalum (Ta) or their compound such as TiN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, not being limited thereto.”).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al, US 20230352529 A1 (Jo) in view of Wu et al, US 20210202323 A1 (Wu) in further view of Zhang et al, US 10763177 B1 (Zhang) in further view of M. G. Bardon et al., "Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells," 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 2018, pp. 143-144, doi: 10.1109/VLSIT.2018.8510633, (Bardon).
Regarding claim 2; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 1.
However, Jo in view of Wu in further view of Zhang does not teach wherein the distance between each of the plurality of second nanosheet channel layers is from about 1 to about 3 nanometers (nm) less than the distance between each of the plurality of first nanosheet channel layers.
Bardon teaches wherein the distance between each of the plurality of second nanosheet channel layers (Bardon: Annotated Fig (1) shared in this OA: Nanosheet) is from about 1 to about 3 nanometers (nm) less than the distance between each of the plurality of first nanosheet channel layers (Fig (1); Conclusion section of Bardon).
Jo in view of Wu in further view of Zhang and Bardon are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jo in view of Wu in further view of Zhang by making the difference in the spacing between the second set of nanosheet channel layers and the first set of the nanosheet channel layers between 1 nm and 3 nm to retain the insulation between the different channel layers leading to a more reliable device.
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Regarding claim 12; Jo in view of Wu in further view of Zhang teaches all the limitations of the semiconductor structure according to claim 11.
However, Jo in view of Wu in further view of Zhang does not teach wherein the distance between each of the plurality of second nanosheet channel layers is from about 1 to about 3 nanometers (nm) less than the distance between each of the plurality of first nanosheet channel layers.
Bardon teaches wherein the distance between each of the plurality of second nanosheet channel layers (Bardon: Annotated Fig (1) shared in this OA: Nanosheet) is from about 1 to about 3 nanometers (nm) less than the distance between each of the plurality of first nanosheet channel layers (Fig (1); Conclusion section of Bardon).
Jo in view of Wu in further view of Zhang and Bardon are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim in view of Wu in further view of Zhang by making the difference in the spacing between the second set of nanosheet channel layers and the first set of the nanosheet channel layers between 1 nm and 3 nm to retain the insulation between the different channel layers leading to a more reliable device.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Bao et al, US 20230170352 A1 (Bao); discloses two nanosheet transistors stacked vertically.
Zhang et al, US 10879352 B2 (Zhang); discloses two nanosheet transistors stacked vertically with an insulating layer in between the devices.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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