Prosecution Insights
Last updated: May 29, 2026
Application No. 18/527,890

METHOD OF MANUFACTURING A SILICON BIPOLAR JUNCTION TRANSISTOR, AND A BJT

Non-Final OA §102§112
Filed
Dec 04, 2023
Priority
Jan 06, 2023 — EU 23150548.8
Examiner
HO, ANTHONY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nxp B V
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1026 granted / 1130 resolved
+22.8% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
26 currently pending
Career history
1160
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
52.6%
+12.6% vs TC avg
§102
22.4%
-17.6% vs TC avg
§112
10.3%
-29.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1130 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group II, claims 7-17, in the reply filed on March 4, 2026 is acknowledged. Accordingly, claims 1-6 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 4, 2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on December 4, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 7-17 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without the necessary prior processing steps, as disclosed, for example, in paragraphs 0013, 0032, 0053, and the necessary subsequent processing steps, as disclosed, for example, in paragraphs 0017, 0032, 0045, 0049, 0050, 0055, 0056, 0061-0063, 0070-0072, which is/are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976). The claimed “prior processing steps” and “subsequent processing steps” as recited in claim 7 are critical or essential because without the prior processing steps or subsequent processing steps, one of ordinary skill in the art would not be enabled to reproduce the claimed method. Claims 8-17 are rejected based on their dependency on claim 7. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 7-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: “prior processing steps” and “subsequent processing step” as recited in claim 7. The claimed “prior processing steps” and “subsequent processing steps” as recited in claim 7 are critical or essential because without the prior processing steps or subsequent processing steps, one of ordinary skill in the art would not be able to define the metes and bounds of the claimed method. Claims 8-17 are rejected based on their dependency on claim 7. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 7, 9, 14, and 15, as best understood, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Johnson et al (US Patent 5,593,905). In re claim 7, Johnson et al discloses a method of manufacturing a silicon bipolar junction transistor device, the method comprising a sequence of steps including: prior processing steps (i.e. see at least Figures 5 and 6); depositing a polysilicon layer (i.e. 114) over at least a device region (i.e. see at least Figure 7); depositing a dielectric layer (i.e. 122) over the polysilicon layer (i.e. see at least Figure 7); patterning a photoresist layer (i.e. see at least column 3, lines 46-51) and etching a window (i.e. emitter window) in the dielectric layer and the polysilicon layer through an opening in the photoresist layer (i.e. see at least Figure 7); patterning a further photoresist layer (i.e. see at least column 4, lines 22-25) to expose at least the window; etching a layer stack comprising SiGe (i.e. 118, 119, see at least column 3, lines 37-45 disclosing the use of SiGe) through the window (i.e. see at least Figure 8), to expose a silicon layer (i.e. 102) thereunder; doping the silicon layer by ion implantation (i.e. see at least column 5, lines 10-12) through the window to form a base region (i.e. 108); and subsequent processing steps (i.e. see at least Figure 4; column 5, lines 12-23). In re claim 9, Johnson et al discloses overdoping a part of the base region to form an emitter region (i.e. 126). In re claim 14, Johnson et al discloses wherein etching a layer stack comprising SiGe through the window is performed using an anisotropic etching process (i.e. see at least column 4, line 59 to column 5, line 9). In re claim 15, Johnson et al discloses depositing a further dielectric layer (i.e. 130) and etching an opening in the further dielectric layer in the bottom of the window (i.e. see at least Figure 9). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY HO/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Dec 04, 2023
Application Filed
May 20, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.4%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1130 resolved cases by this examiner. Grant probability derived from career allowance rate.

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