DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 17 and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 17 recites “an N-over-N driver and a P-over-N driver for the line in a third voltage domain.” Examiner notes that Applicant’s Figure 10 and corresponding paragraph [0049] of the specification describe either an N-over-N driver or a P-over-N driver, but does not support the limitation of both an N-over-N driver and a P-over-N driver as recited in claim 17. For the purposes of examination, the limitation has been treated as “one of an N-over-N driver and a P-over-N driver” to agree with Applicant’s original disclosure.
Claim 18 is rejected for being dependent on claim 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boerstler et al. (U.S. Patent 8,736,304, hereafter Boerstler) in view of Welty (U.S. Patent 7,667,519).
Claim 1: Boerstler teaches a circuit (Figure 3) for communicating a signal (311) over a first line (to 319), the circuit comprising:
a transmitter (302) configured to generate the signal in a first voltage domain (VDDA);
a first line driver (304) comprising:
a P-over-N driver (312 over 314) configured to receive the signal in the first voltage domain (from 302) and to output the signal on the first line (320) in a second voltage domain (VDDMID).
Boerstler does not specifically teach a feed-forward pull-up transistor.
Welty teaches a level translator circuit (Figure 4) comprising a driver (N3, P2-P6) and a feed-forward pull-up transistor (N2) coupled to the first line (BIAS corresponding to 320 of Boerstler) and configured to pull-up to the second voltage domain (VCCB corresponding to VDDMID of Boerstler), a gate of the feed-forward pull-up transistor configured to be driven by a signal in the first voltage domain (boost connected to the inputs of the driver N3, P2-P6 via the intervening circuitry between the inverted ENABLE signal and boost, which corresponds to the input signal 311 in Boerstler in the VDDA domain).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the pull-up transistor taught by Welty in the circuit of Boerstler to minimize overshoot or undershoot at the output while providing enough drive to charge up the output quickly (column 4 lines 50-53).
Claim 2: The combined circuit further teaches a receiver (304 of Boerstler) configured to receive the signal in the second voltage domain (VDD).
Claim 3: The combined circuit further teaches the receiver (304 of Boerstler) is configured to operate in the second voltage domain (where the first domain is VDDA and the second voltage domain includes VDDMID and VDD).
Claim 4: The combined circuit further teaches the receiver comprising an inverter-based topology (304; column 4 lines 34-42).
Claim 5: The combined circuit further teaches a level shifter (P8, N4 of Welty) coupled to the inverter-based topology via a second line (second line coupled to the output).
Claim 6: The combined circuit further teaches that the level shifter is configured to shift a voltage of the signal from the second voltage domain to the first voltage domain (column 4 lines 32-33 of Boerstler).
Claim 7: The combined circuit further teaches that the receiver is configured to operate in a third voltage domain (VDD).
Claim 8: The combined circuit further teaches that the transmitter is part of a first chip (320 of Boerstler) and the receiver is part of a second chip (322 of Boerstler).
Claim 9: Boerstler teaches a circuit (Figure 3) for serial communication of signals (311) over a line (to 319), the circuit comprising:
a transmitter (302) configured to generate the signal in a first voltage domain (VDDA);
a driver circuit (304) for the line comprising:
a PFET pull-up path (312) and NFET pull-down path (314) arranged in parallel to a second voltage domain (VDDMID).
Boerstler does not specifically teach an NFET feed-forward path.
Welty teaches a level translator circuit (Figure 4) comprising a driver (N3, P2-P6) and an NFET feed-forward path (path between the inverted ENABLE signal and N2) for the signals configured to boost a transition of the signals from lower to higher voltage levels (to VCCB, corresponding to VDDMID of Boerstler) on the line (BIAS corresponding to 320 of Boerstler) via a direct connection to the signals on the line in the first voltage domain (inverted ENABLE signal corresponding to input signal 311 of Boerstler in the VDDA domain).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the pull-up transistor taught by Welty in the circuit of Boerstler to minimize overshoot or undershoot at the output while providing enough drive to charge up the output quickly (column 4 lines 50-53).
Claim 10: The combined circuit further teaches a receiver (304 of Boerstler) configured to receive the signals in the second voltage domain (where the second voltage domain contains VDDMID and VDD).
Claim 11: The combined circuit further teaches that the receiver is configured to operate in the second voltage domain (where the second voltage domain contains VDDMID and VDD).
Claim 12: The combined circuit further teaches that the receiver comprises an inverter-based topology (304 of Boerstler).
Claim 13: The combined circuit further teaches that transmitter further comprises a level shifter coupled to the inverter-based topology (P8, N4 of Welty coupled to the output of 302 of Boerstler).
Claim 14: The combined circuit further teaches that the level shifter is configured to shift a voltage of the signal from the second voltage domain to the first voltage domain (column 4 lines 32-33 of Boerstler).
Claim 15: The combined circuit further teaches that the receiver is configured to operate in a third voltage domain (VDD).
Claim 16: The combined circuit further teaches that the transmitter is part of a first chip (320 of Boerstler) and the receiver is part of a second chip (322 of Boerstler).
Claim 19: The combined circuit further teaches that an input to a driver of the feed-forward pull-up transistor (circuitry between the inverted ENABLE signal and N2 of Welty) is directly connected to a data signal line in the first voltage domain (the inverted ENABLE signal corresponds to the input signal 311 of Boerstler that is in the VDDA domain).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable Applicant’s Prior Art Figure 9 (hereafter APA) in view of Boerstler.
Claim 17: APA teaches a transceiver circuit (Figure 9) comprising:
a transmitter (connected to TXDAT) in a first voltage domain (VTX) AC-coupled (via 904) to a receiver (coupled to RXDAT) in a second voltage domain (VRX) over a line (LINE);
the receiver comprising a pair of inverter stages (inverters connected to VRX) arranged along the line (to RXDAT), with negative feedback (- feedback) to a first inverter stage of the pair and positive feedback to both inverter stages (+ feedback).
APA does not specifically teach one of an N-over-N driver and P-over-N driver in a third voltage domain.
Boerstler teaches one of an N-over-N driver and P-over-N driver (304 is P-over-N) for the line in a third voltage domain (VDDMID), the N-over-N driver or P-over-N driver configured to receive a signal in a first voltage domain of the transmitter (311) and to output the signal on the line in the third voltage domain (VDDMID).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the driver taught by Boerstler in the circuit of APA to preserve the duty cycle when translating a signal between voltage domains (column 4 lines 25-27).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over APA in view of Boerstler and further in view of Reddy et al. (U.S. Patent 10,951,441, hereafter Reddy).
Claim 18: APA and Boerstler teach the limitations of claim 17 above. APA and Boerstler do not specifically teach a capacitor that is proximity based toward the receiver.
Reddy teaches a receiver system (Figure 2), wherein the transmitter is AC-coupled to the receiver via a capacitor that is proximity biased toward the receiver on the line (AC-coupling capacitors are on the RX side of the line).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the capacitors taught by Reddy in the circuit of APA and Boerstler to enable AC-coupling and DC-coupling mode reception through an AC-coupling capacitor (column 1 lines 37-45).
Response to Arguments
Applicant's arguments filed January 9, 2026 have been fully considered but they are not persuasive.
Regarding claims 1-16, Applicant asserts that the NFET of Welty cannot be combined with Boerstler. Examiner respectfully disagrees. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the pull-up transistor taught by Welty in the circuit of Boerstler to minimize overshoot or undershoot at the output while providing enough drive to charge up the output quickly (column 4 lines 50-53).
Regarding claim 17, Applicant asserts that Boerstler does not teach an N-over-N driver and a P-over-N driver for the line in a third voltage domain. Examiner respectfully refers to the rejection under 35 U.S.C. 112(a) as stated above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.J.O/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
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