DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of applicant’s Amendment, filed 01 December 2025. The changes and remarks disclosed therein have been considered.
No claims have been cancelled/added by Amendment. Therefore, claims 1-20 are pending in the application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. See MPEP 606.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 9-20’s “peripheral circuit” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 9-10, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 7,433,231 B2) in view of Uchimura (US 12,211,558 B2) and further in view of Lee et al (US 12,190,954 B2 hereinafter “Lee”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Aritome, for example in Figs. 1-10, discloses a method for operating (see for example in Figs. 3, 8 related in Figs. 1-2, 4-7, 9-10) a memory (see for example in Figs. 9-10 related in Figs. 1-8), wherein the memory includes a plurality of memory strings (see for example in Figs. 1-2 related in Figs. 3-10), a memory string (see for example in Figs. 3, 8 related in Figs. 1-2, 4-7, 9-10) includes a plurality of memory cells (via WL-0 to WL-31; in Figs. 3-4 related in Figs. 1-2, 5-10) and plurality of select gates (e.g., SGD-0, SGD-1, SGS-0, SGS-1; in Figs. 3-4 related in Figs. 1-2, 5-10), a memory cell (e.g., memory cell 208-1; in Figs. 2-3 related in Figs. 1, 4-10) is coupled to a word line (e.g., WL-0 to WL-31; in Figs. 3-4 related in Figs. 1-2, 5-10) and a bit line (e.g., 104/204/BL; in Figs. 1-4 related in Figs. 5-10), and a select gate is coupled to a select line (via SGD-0, SGD-1, SGS-0, SGS-1; in Figs. 3-4 related in Figs. 1-2, 5-10), the method including: during an erase phase (e.g., ERASE; in Fig. 3 related in Figs. 1-2, 4-10), applying an erase voltage to the word line (e.g., 0V; in Fig. 3 related in Figs. 1-2, 4-10); applying the erase voltage to the select line coupled to a target select gate (e.g., SGS-1; in Fig. 3 related in Figs. 1-2, 4-10) from the plurality of select gates (e.g., SGD-0, SGD-1, SGS-0, SGS-1; in Figs. 3-4 related in Figs. 1-2, 5-10); and during a program phase (e.g., PROGRAM (WL-1); in Fig. 3 related in Figs. 1-2, 4-10) for select gate (e.g., WL-1; in Fig. 3 related in Figs. 1-2, 4-10), applying a pass voltage to the word line (e.g., Vpass; in Fig. 3 related in Figs. 1-2, 4-10). Aritome discloses driving the bit line with 1.0V erase verify voltage (see for example in Fig. 3 related in Figs. 1-2, 4-10).
However, Aritome is silent with regard to driving the bit line with a non-zero second erase voltage.
In the same field of endeavor, Uchimura, for example in Figs. 1-20, discloses driving the bit line a non-zero second erase voltage (e.g., V1 or VERA0; in Figs. 9, 14-20 related in Figs. 1-8, 10-13).
The above Aritome/Uchimura, combination discloses the claimed invention as discussed above. However, the above Aritome/Uchimura is silent with regard to applying a program voltage to the select line coupled to the target select gate.
In the same field of endeavor, Lee, for example in Figs. 1-13, discloses to applying a program voltage (e.g., Vpgm1; in Figs. 3-4 related in Figs. 1-2, 5-13) to the select line coupled to the target select gate (e.g., GSL; in Figs. 3-4 related in Figs. 1-2, 5-13).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Aritome such as multiple select gates with non-volatile memory cells (see for example in Figs. 1-10 of Aritome) and the teaching of Uchimura such as semiconductor storage device (see for example in Figs. 1-20 of Uchimura) by incorporating the teaching of Lee such as memory device and program method of ground select transistors (see for example in Figs. 1-13 of Lee), for the purpose of controlling the program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell (Lee, see Abstract).
Regarding claim 2, the above Aritome/Uchimura/Lee, the combination discloses wherein an erase-verify phase is further included after the erase phase and before the program phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above), and the method further includes: during the erase-verify phase, applying a first verify voltage to the select line coupled to the target select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above).
Regarding claim 8, the above Aritome/Uchimura/Lee, the combination discloses wherein a pre-program phase is further included before the erase phase (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above), and the method further includes: during the pre-program phase, applying a pre-program voltage or the pass voltage to the word line, and applying the pre-program voltage to the select line coupled to the target select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above).
Regarding Independent Claim 9, Aritome, for example in Figs. 1-10, discloses a memory (see for example in Figs. 9-10 related in Figs. 1-8), comprising: an array of memory cells (e.g., 200; in Fig. 2 related in Figs. 1, 3-10); and a peripheral circuit coupled to the array of memory cells (e.g., 906, 908, 910, 912, 914, 916; in Fig. 9 related in Figs. 1-8, 10), and is configured to: during an erase phase (e.g., ERASE; in Fig. 3 related in Figs. 1-2, 4-10), apply an erase voltage to a word line (e.g., 0V; in Fig. 3 related in Figs. 1-2, 4-10); apply the erase voltage to a select line coupled to a target select gate (e.g., SGS-1; in Fig. 3 related in Figs. 1-2, 4-10) from a plurality of select gates (e.g., SGD-0, SGD-1, SGS-0, SGS-1; in Figs. 3-4 related in Figs. 1-2, 5-10); and during a program phase for select gate (e.g., PROGRAM(WL-1); in Fig. 3 related in Figs. 1-2, 4-10), apply a pass voltage to the word line (e.g., Vpass; in Fig. 3 related in Figs. 1-2, 4-10).
However, Aritome is silent with regard to driving the bit line with a non-zero second erase voltage.
In the same field of endeavor, Uchimura, for example in Figs. 1-20, discloses driving the bit line a non-zero second erase voltage (e.g., V1 or VERA0; in Figs. 9, 14-20 related in Figs. 1-8, 10-13).
The above Aritome/Uchimura, combination discloses the claimed invention as discussed above. However, the above Aritome/Uchimura is silent with regard to applying a program voltage to the select line coupled to the target select gate.
In the same field of endeavor, Lee, for example in Figs. 1-13, discloses to applying a program voltage (e.g., Vpgm1; in Figs. 3-4 related in Figs. 1-2, 5-13) to the select line coupled to the target select gate (e.g., GSL; in Figs. 3-4 related in Figs. 1-2, 5-13).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Aritome such as multiple select gates with non-volatile memory cells (see for example in Figs. 1-10 of Aritome) and the teaching of Uchimura such as semiconductor storage device (see for example in Figs. 1-20 of Uchimura) by incorporating the teaching of Lee such as memory device and program method of ground select transistors (see for example in Figs. 1-13 of Lee), for the purpose of controlling the program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell (Lee, see Abstract).
The structure in of prior art (Aritome, Uchimura and Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 10, the above Aritome/Uchimura/Lee, the combination discloses wherein an erase-verify phase is further included after the erase phase and before the program phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above), and the peripheral circuit is further configured to: during the erase-verify phase, apply a first verify voltage to the select line coupled to the target select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above). Also, the structure in of prior art (Aritome, Uchimura and Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 16, the above Aritome/Uchimura/Lee, the combination discloses wherein a pre-program phase is further included before the erase phase (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above), and the peripheral circuit is further configured to: during the pre-program phase (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above), apply a pre-program voltage or the pass voltage to the word line (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above), and apply the pre-program voltage to the select line coupled to the target select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above). Also, the structure in of prior art (Aritome, Uchimura and Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 17, Aritome, for example in Figs. 1-10, discloses a memory system (see for example in Figs. 9-10 related in Figs. 1-8), including: a memory controller (e.g., 912/1020; in Figs. 9-10 related in Figs. 1-8) configured to control a memory to write data or to read data stored in the memory (e.g., 902; in Figs. 9-10 related in Figs. 1-8); and the memory, including: an array of memory cells (e.g., 200; in Figs. 2-4 related in Figs. 1, 5-10); and a peripheral circuit coupled to the array of memory cells (e.g., 906, 908, 910, 912, 914, 916; in Fig. 9 related in Figs. 1-8, 10), and configured to: during an erase phase (e.g., ERASE; in Fig. 3 related in Figs. 1-2, 4-10), apply an erase voltage to a word line (e.g., 0V; in Fig. 3 related in Figs. 1-2, 4-10); apply the erase voltage to a select line coupled to a target select gate (e.g., SGS-1; in Fig. 3 related in Figs. 1-2, 4-10) from a plurality of select gates (e.g., SGD-0, SGD-1, SGS-0, SGS-1; in Figs. 3-4 related in Figs. 1-2, 5-10); and during a program phase for select gate (e.g., PROGRAM(WL-1); in Fig. 3 related in Figs. 1-2, 4-10), apply a pass voltage to the word line (e.g., Vpass; in Fig. 3 related in Figs. 1-2, 4-10).
However, Aritome is silent with regard to driving the bit line with a non-zero second erase voltage.
In the same field of endeavor, Uchimura, for example in Figs. 1-20, discloses driving the bit line a non-zero second erase voltage (e.g., V1 or VERA0; in Figs. 9, 14-20 related in Figs. 1-8, 10-13).
The above Aritome/Uchimura, combination discloses the claimed invention as discussed above. However, the above Aritome/Uchimura is silent with regard to applying a program voltage to the select line coupled to the target select gate.
In the same field of endeavor, Lee, for example in Figs. 1-13, discloses to applying a program voltage (e.g., Vpgm1; in Figs. 3-4 related in Figs. 1-2, 5-13) to the select line coupled to the target select gate (e.g., GSL; in Figs. 3-4 related in Figs. 1-2, 5-13).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Aritome such as multiple select gates with non-volatile memory cells (see for example in Figs. 1-10 of Aritome) and the teaching of Uchimura such as semiconductor storage device (see for example in Figs. 1-20 of Uchimura) by incorporating the teaching of Lee such as memory device and program method of ground select transistors (see for example in Figs. 1-13 of Lee), for the purpose of controlling the program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell (Lee, see Abstract).
The structure in of prior art (Aritome, Uchimura and Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 18, the above Aritome/Lee, the combination discloses wherein an erase-verify phase is further included after the erase phase and before the program phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above), and the peripheral circuit is further configured to: during the erase-verify phase, apply a first verify voltage to the select line coupled to the target select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above). Also, the structure in of prior art (Aritome, Uchimura and Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Claims 3-7, 11-15, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 7,433,231 B2) and Uchimura (US 12,211,558 B2) in view of Lee et al (US 12,190,954 B2 hereinafter “Lee”) and further in view of Nam et al (US 10,163,511 B2 hereinafter “Nam”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 3, the above Aritome/Uchimura/Lee, the combination discloses wherein the select gate includes a top select gate and a bottom select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above), and the target select gate is the bottom select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome with Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura and also see in Figs. 1-13 of Lee, as discussed above). The above Aritome/Uchimura/Lee, the combination discloses the claimed invention as discussed above. However, the above Aritome/Uchimura/Lee is silent with regard to the method further includes: during the program phase for select gate, applying a program select voltage to the top select gate of the memory string at which the target select gate is located, and applying a program prohibition voltage to the top select gates of other memory strings.
In the same field of endeavor, Nam, for example in Figs. 1-13, discloses during the program phase for select gate, applying a program select voltage (e.g., T_PGM; in Fig. 3 related in Figs. 1-2, 4-13) to the top select gate of the memory string at which the target select gate is located (see for example in Figs. 3, 5-6 related in Figs. 1-2, 4, 7-13), and applying a program prohibition voltage to the top select gates of other memory strings (see for example in Figs. 3, 5-6 related in Figs. 1-2, 4, 7-13).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Aritome such as multiple select gates with non-volatile memory cells (see for example in Figs. 1-10 of Aritome), the teaching of Uchimura such as semiconductor storage device (see for example in Figs. 1-20 of Uchimura) and the teaching of Lee such as memory device and program method of ground select transistors (see for example in Figs. 1-13 of Lee) by incorporating the teaching of Nam such as nonvolatile memory device and storage device including nonvolatile memory device (see for example in Figs. 1-13 of Nam), for the purpose of controlling the programming string selection transistors or ground selection transistors of the selected memory block, and performing a verification by using a verification voltage (Nam, see Abstract).
Regarding claim 4, the above Aritome/Uchimura/Lee/Nam, the combination discloses wherein a program-verify phase for select gate is further included after the program phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and the method further includes: during the program-verify phase for select gate, applying a second verify voltage to the select line coupled to the target select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above); and increasing the program voltage in response to a threshold voltage of the target select gate not reaching a target threshold voltage (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura and Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Aritome/Uchimura/Lee/Nam, the combination discloses further including: during the program-verify phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), applying a program select voltage to the top select gate of the memory string at which the target select gate is located (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and applying a pass voltage to the top select gates of other memory strings (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 6, the above Aritome/Uchimura/Lee/Nam, the combination discloses further including: during the program-verify phase for select gate, applying the pass voltage to the word line (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 7, the above Aritome/Uchimura/Lee/Nam, the combination discloses further including: during the erase phase, applying a hold & release voltage to the top select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 11, the above Aritome/Uchimura/Lee/Nam, the combination discloses wherein the select gate includes a top select gate and a bottom select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and the target select gate is the bottom select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and the peripheral circuit is further configured to: during the program phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), apply a program select voltage to the top select gate of a memory string at which the target select gate is located (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and apply a program prohibition voltage to the top select gates of other memory strings (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 12, the above Aritome/Uchimura/Lee/Nam, the combination discloses wherein a program-verify phase for select gate is further included after the program phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and the peripheral circuit is further configured to: during the program-verify phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), apply a second verify voltage to the select line coupled to the target select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above); and increase the program voltage in response to a threshold voltage of the target select gate not reaching a target threshold voltage (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 13, the above Aritome/Uchimura/Lee/Nam, the combination discloses wherein the select gate further includes a top select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and the peripheral circuit is further configured to: during the program-verify phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), apply a program select voltage to the top select gate of the memory string at which the target select gate is located (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and apply the pass voltage to the top select gates of other memory strings (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 14, the above Aritome/Uchimura/Lee/Nam, the combination discloses wherein the peripheral circuit is further configured to: during the program-verify phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), apply the pass voltage to the word line (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 15, the above Aritome/Uchimura/Lee/Nam, the combination discloses wherein the peripheral circuit is further configured to: during the erase phase, apply a hold & release voltage to the top select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 19, the above Aritome/Uchimura/Lee/Nam, the combination discloses wherein the select gate includes a top select gate and a bottom select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and the target select gate is the bottom select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and the peripheral circuit is further configured to: during the program phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), apply a program select voltage to the top select gate of a memory string at which the target select gate is located (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and apply a program prohibition voltage to the top select gates of other memory strings (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Regarding claim 20, the above Aritome/Uchimura/Lee/Nam, the combination discloses wherein a program-verify phase for select gate is further included after the program phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), and the peripheral circuit is further configured to: during the program-verify phase for select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above), apply a second verify voltage to the select line coupled to the target select gate (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above); and increase the program voltage in response to a threshold voltage of the target select gate not reaching a target threshold voltage (see for example in Figs. 3-4 related in Figs. 1-2, 5-10 of Aritome, in Figs. 9, 14-20 related in Figs. 1-8, 10-13 of Uchimura, with Figs. 1-13 of Lee and also see in Figs. 1-13 of Nam, as discussed above). Also, the structure in of prior art (Aritome, Uchimura, Lee and Nam) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from prior art apparatus. MPEP 2114(II).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection is made in view of Uchimura (US 12,211,558 B2).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THA-O H BUI/Primary Examiner, Art Unit 2825 02/05/2026