Number 1
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “28” has been used to designate both a polycrystalline layer (labeled correctly, shown Figs. 1b and 4E-4F) and a spacer layer (incorrectly labeled in Figs. 2-3). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1, 2 and 18 are objected to because of the following informalities:
Claim 1 cites “A structure comprises:” which should read “A structure comprising:”.
Claim 2 cites “the first dopant type is an n-type dopant” which should read “the first dopant type is n-type” as a dopant type is conventionally n-type or p-type.
Claim 18 cites “above the n-SiGe” which should read “above the n-SiGe material.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claims 1 and 20, the limitation "the first polycrystalline layer" has insufficient antecedent basis. The instant application describes a polycrystalline material (28, shown Fig. 2) vertically contacting a first semiconductor layer (20) which is doped oppositely to a second semiconductor material (24a). The device further comprises at least a second polycrystalline material 24b which is doped identical to 24a. Claim 5 further cites the polycrystalline material being p-type and the second semiconductor material being n-type as drawn to the embodiment of Fig. 2. Claim 8 further describes the polycrystalline material being n-type and the second semiconductor material being p-type as drawn to the embodiment of Fig. 3.
For examination purposes, the first polycrystalline layer is interpreted as “the polycrystalline material” vertically contacting the first semiconductor layer.
Claims 2-11 are further rejected due to their dependence on claim 1 and lack of further clarity regarding “the first polycrystalline layer.”
Regarding Claim 12, the limitation “the doped semiconductor material actings as base of the heterojunction bipolar transistor and which is isolated from an underlying well of a same dopant type” lacks clarity regarding which feature comprises “a same dopant type” and whether only the base of the heterojunction bipolar transistor is intended to be isolated from an underlying well or the entire heterojunction bipolar transistor is intended to be isolated.
For examination purposes, the base of the HBT is interpreted as N-SiGe region 22 which is isolated from an N-well 19 by p-type region 14 (as drawn to the embodiment of Fig. 2), wherein the base is isolated from the N-well by a sub-collector of the HBT (p-type region 14).
Claims 13-19 are further rejected due to their dependence on claim 12 and lack of further clarity.
Regarding Claims 17 and 19, the limitation “the SCR” lacks antecedent basis. For examination purposes, “the SCR” is interpreted as the “silicon controlled rectifier.”
Allowable Subject Matter
Claims 1-20 comprise allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, Du (Vertical Bipolar Junction Transistor Triggered Silicon-Controlled Rectifier for Nanoscale Engineering, 2020) being the most relevant prior art of record teaches a structure (see Fig. 1b) comprising:
a first region (N-well) comprising a first dopant type (n-type) provided in a semiconductor substrate (P-epi);
a second region (P-well) comprising a second dopant type (p-type) provided in the semiconductor substrate;
an isolation region (STI) between the first region and the second region;
a first semiconductor layer (P-ESD) vertically contacting the first region, the first semiconductor layer having a dopant type opposite from the first dopant type (shown Fig. 1b);
a second semiconductor layer (N+ region above second region) vertically contacting the second region, the second semiconductor layer having a dopant type opposite from the second dopant type (shown Fig. 1b);
a material vertically contacting the first semiconductor layer (N+ layer above P-ESD); and
a conductive bridge vertically contacting the first semiconductor layer and electrically connected to the second semiconductor layer (shown schematically in Fig. 1b).
Du is silent regarding a crystalline morphology of the semiconductor layers and does not teach a polycrystalline semiconductor material in vertical contact with the first semiconductor layer and the second semiconductor layer.
Mishra (US 20190237568 A1) teaches a silicon controlled rectifier integrated into a heterojunction bipolar transistor process (see Figs. 7A and 8) a first region (16) comprising a first dopant type (p-type) provided in a semiconductor substrate (14);
a second region (18) comprising a second dopant type (n-type) provided in the semiconductor substrate;
an isolation region (20) between the first region and the second region;
a first semiconductor layer (26a) vertically contacting the first region;
a second semiconductor layer (26b) vertically contacting the second region, the second semiconductor layer having a dopant type opposite from the second dopant type (layer 26 having a p-type dopant);
a material vertically contacting the first semiconductor layer (52); and
a single crystal section (35) in vertical contact with the second semiconductor layer.
The prior art does not explicitly teach or suggest in any combination a polycrystalline material vertically contacting the first semiconductor layer and a second semiconductor material having an opposite doping type of the polycrystalline material and vertically contacting the first semiconductor layer and the second semiconductor layer (i.e., layer 24a and 24b shown Fig. 2 of the instant application, which bridges the first semiconductor material and the second semiconductor material).
As such, claim 1 is determined to have patentable subject matter. Claims 2-11 and 20 would further be patentable as they require all limitations of claim 12.
Regarding Claim 12, Du (Vertical Bipolar Junction Transistor Triggered Silicon-Controlled Rectifier for Nanoscale Engineering, 2020) being the most relevant prior art of record teaches a structure (see Fig. 1b) comprising a heterojunction bipolar transistor (BJT, see also annotated n-well:p-ESD:N+ in Fig. 1b and “Introduction” which suggests implementing a heterojunction bipolar transistor to reduce trigger voltage of the SCR) integrated with a silicon controlled rectifier (VBTSCR, see p-n-p-n path shown in Fig. 1b) which share a doped semiconductor material (N+ region above P-ESD, interpreted broadly to mean that the device structure “shares” said material) above an underlying semiconductor substrate (P-epi), and which is isolated from an underlying well (N-well) of a same dopant type by an opposite dopant type region (P-ESD) in the underlying semiconductor substrate (shown Fig. 1b).
Mishra (US 20190237568 A1) teaches a silicon controlled rectifier integrated into a heterojunction bipolar transistor process (see Figs. 7A and 8) which comprises a heterojunction bipolar transistor (60, shown Fig. 7A) in a separate region from a silicon controlled rectifier (54, shown Fig. 8), wherein the heterojunction bipolar transistor has a base (26c) which is a shared material layer with the silicon controlled rectifier (shared with 26a and 26b). However, Mishra teaches away from Du in that the base of the heterojunction bipolar transistor is not separated from an underlying well of a same dopant type by a region comprising an opposite dopant type. Mishra teaches that an underlying well of an opposite dopant type is implemented to form a lower p-n junction (17) of the heterojunction bipolar transistor.
The prior art does not explicitly teach or suggest in any combination a shared doped semiconductor material acting as base of the heterojunction bipolar transistor (i.e., the n-type SiGe layer 22 shown in Fig. 2 of the instant application).
As such, claim 12 is determined to have patentable subject matter. Claims 13-19 would further be patentable as they require all limitations of claim 12.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Du (CN 107731811 A) teaches a vertical BJT triggering of SCR devices for ESD protection.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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