Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 3/13/26 has been entered.
Response to Arguments
Applicant’s arguments with regard to the amendment have been fully considered and the newly added limitations are further rejected as set forth below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-8, 10, 12-18, 24, 26 and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 20190006200).
Regarding claim 1. Lin discloses A method of embedding a bare die 36 [0021] in a carrier laminate 32/23/22/20, the method comprising:
providing the bare die comprising a metal layer 42 [0022] on a front side (top side) of the bare die (Fig 5) or on a back side of the bare die opposite the front side;
forming a layer 44 [0022] on the metal layer (Fig 5);
mounting the bare die in a recess (Fig 5: between left 32 and right 32) of the carrier laminate with the layer facing an opening (center opening) of the recess (Fig 5);
filling the recess and covering the layer with a dielectric material 48 [0024] (Fig 6);
removing a portion of the dielectric material to expose the layer on the metal layer (Fig 7);
depositing a metal structure 54 [0024] over the exposed layer on the metal layer and at least a portion of the carrier laminate (Fig 9).
Regarding claim 7. Lin discloses The method of claim 1,
wherein a total thickness of the bare die including the layer is thicker than a depth of the recess (Fig 5: refer to top surface of 44 which is higher than the top surface of 32).
Regarding claim 8. Lin discloses The method of claim 1,
wherein a thickness of the layer is larger than a thickness of the metal layer (Fig 5: whole area of 44 is completely surrounded by 44, and top surface of 42 is lower than the top surface 44).
Regarding claim 10. Lin discloses The method of claim 1, wherein the forming the layer over the metal layer comprises plating, laminating, printing and/or coating (44 is polyimide [0022], which means polyimide on metal contact is inherently and commonly formed by coating processes. Because polyimide is typically applied in its precursor form (polyamic acid) and then cured, the process naturally results in a strong, conformal, and often adhesive contact with metallic surfaces).
Regarding claim 12. Lin discloses The method of claim 1,
wherein the filling the recess with the dielectric material comprises arranging the dielectric material to extend beyond the layer and to at least partially cover the layer (Fig 6).
Regarding claim 13. Lin discloses The method of claim 1,
wherein the removing a portion of the dielectric material that is on the layer comprises grinding [0025], laser ablation or light deterioration.
Regarding claim 14. Lin discloses The method of claim 1,
wherein the mounting the bare die in the recess comprises arranging the bare die on a temporary carrier 20 (Fig 5, [0033]).
Regarding claim 15. Lin discloses The method of claim 14, further comprising:
after the arranging the dielectric, removing the temporary carrier (Fig 15).
Regarding claim 16. Lin discloses The method of claim 1,
the bare die further comprising a further metal layer 78 [0042] on the side of the bare die opposite the metal layer (Fig 17).
Regarding claim 17. Lin discloses The method of claim 16, further comprising:
arranging a further layer 208 over the further metal layer (Fig 18).
Regarding claim 18. Lin discloses The method of claim 17,
wherein the further layer is of a same material as the layer ([0024]: 208 is molding underfill which is polymer [0024], [0022]: 44 is polymer. Thus, they are polymer material):
Regarding claim 24. Lin discloses The method of claim 1, further comprising:
arranging a thick metal layer 70 over the metal layer (Fig 12).
Regarding claim 26. Lin discloses The method of claim 1,
wherein the metal layer comprises copper [0022] or aluminum.
Regarding claim 28. (New) Lin discloses The method of claim 1, wherein forming the layer on the metal layer includes forming the layer only on the metal layer (Fig 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 6 rejected under 35 U.S.C. 103 as being unpatentable over by Lin (US 20190006200) in view of Huang (US 20160276248).
Regarding claim 2. Lin discloses The method of claim 1. But Lin does not disclose wherein the layer comprises an electrically conductive layer.
However, Huang discloses the layer 50 comprises an electrically conductive layer [0023] (Fig 8: metal pillars electrically coupled to transistor).
The references, Lin and Huang may be used to show obviousness because they are analogous art, which is directed to method of forming bare die package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin with the specified features of Huang because they are from the same field of endeavor.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use electrically conductive layer as disclosed by Huang within Lin’s method for the purpose of making enhanced device packaging with superior electrical performance, enhanced thermal management, and improved structural reliability. Thereby increases manufacturability.
Regarding claim 6. Lin discloses The method of claim 1. But Lin does not explicitly disclose wherein the layer comprises metal.
However, Huang discloses the layer 50 comprises metal [0023] (Fig 8).
The references, Lin and Huang may be used to show obviousness because they are analogous art, which is directed to method of forming bare die package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin with the specified features of Huang because they are from the same field of endeavor.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use electrically conductive layer as disclosed by Huang within Lin’s method for the purpose of making enhanced device packaging with superior electrical performance, enhanced thermal management, and improved structural reliability. Thereby increases manufacturability.
Claims 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over by Lin (US 20190006200).
Regarding claim 5. Lin discloses The method of claim 1, But Lin does not explicitly disclose wherein removing the layer comprises wet etching, dry etching, plasma etching, or light deterioration.
However, Lin discloses mechanical grinding step [0025]. In the applicant’s field of endeavor, in many industrial applications—particularly in semiconductor fabrication, surface finishing, and material preparation—mechanical grinding is frequently accompanied by or paired with either wet or dry processing to achieve desired results.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Lin’s method includes either wet etching or dry etching for purpose of providing enhanced surface smoothness.
Regarding claim 9. Lin discloses The method of claim 1. But Lin does not explicitly disclose wherein a thickness of the layer is in a range from about 2 μm to about 30 μm.
However, the ordinary artisan would have recognized the claimed thickness range to be a result effective variable affecting to make proper covering an embedded device contact pad are those that dictate electrical insulation (voltage rating/breakdown) and capacitive coupling (parasitic capacitance/signal integrity). Thus, it would have been obvious that the thickness of Lin’s layer within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
It is further noted that the specification contains no disclosure of either the critical nature of instant claimed thickness range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Claims 11 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over by Lin (US 20190006200) in view of Lin (US 20110026232; hereinafter Lin-232).
Regarding claim 11. Lin discloses The method of claim 1. But Lin does not disclose wherein the carrier is a printed circuit board.
However, Lin-232 discloses the carrier is a printed circuit board 11 (Fig 5, [0081]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Lin’s carrier with Lin-232’s printed circuit board for the purpose of providing enhanced high-frequency performance, better heat management, miniaturization, easier assembly/repair, and increased component density, due to shorter electrical paths, direct thermal contact, and standardized designs.
Regarding claim 19. Lin discloses The method of claim 1. But Lin does not disclose wherein the layer comprises an electrically conductive layer formed by sputtered material, a thin-film or a nano-coating.
However, Fig 7 of Lin-232 discloses the layer 34/46 comprises an electrically conductive layer 34 formed by sputtered material, a thin-film or a nano-coating ([0097]/[0102]: 34 is aluminum-copper-alloy layer which is thin film conductive layer embedded in 46. In the applicant’s filed of endeavor, thin metallic layer of aluminum-copper-alloy for embedded conductive pattern in advanced semiconductor packaging is typically formed using Atomic Layer Deposition (ALD) with high level of generality.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Lin’s layer with Lin-232’s conductive layer for the purpose of providing enhanced atomic-level control, conformality, and pinhole-free quality for ultra-thin, high-aspect-ratio features for such low-nanometer thicknesses.
Regarding claim 20. Lin in view of Lin-232 discloses The method of claim 19, Lin-232 discloses wherein a thickness of the layer is smaller than a thickness of the metal layer (Fig 7: the metal layer 36/34a [0104] are embedded in 48 and the conductive layer 34 is embedded in 46. And the 46 and 48 has the same thickness [0097]/[0098]. However, the portion of 36 is protruded from the 48. Thus, a thickness of the layer is smaller than a thickness of the metal layer).
Regarding claim 21. Lin in view of Lin-232 discloses The method claim 19, Lin-232 discloses wherein a thickness of the layer is in a range from about 1 nm to about 2 μm [0097].
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20190006200) in view of Lin (US 20110026232; hereinafter Lin-232), and further in view of Sato (US 11765909).
Regarding claim 22. Lin in view of Lin-232 discloses The method of claim 19, Lin-232 discloses wherein the layer is an atomic layer deposition (ALD) layer ([0097]/[0102]: 34 is aluminum-copper-alloy layer which is thin film conductive layer embedded in 46. In the applicant’s filed of endeavor, thin metallic layer of aluminum-copper-alloy for embedded conductive pattern in advanced semiconductor packaging is typically formed using Atomic Layer Deposition (ALD) with high level of generality. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Lin in view of Lin-232 discloses the claimed feature).
Further, the Lin-232’s layer includes thin SiOC layer [0097]. And in the applicant of endeavor, a thin film SiOC layer is deposited via Atomic Layer Deposition (ALD) is utilized for encapsulating and passivating die surfaces with high level of generality. For example, Fig 7A of Sato discloses ALD deposited layer 708 on the die. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Sato’s ALD deposition within the Lin in view of Lin-232’s method for the purpose of providing enhanced passivation layer or interlayer for stable, and long-term passivation.
Regarding claim 23 Lin in view of Lin-232 and Sato disclose The method of claim 22, Sato discloses wherein the ALD layer covers at least a plurality of sides of the bare die, optionally encapsulating the bare die (Fig 7A).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over by Lin (US 20190006200) in view of Tsai (US 20170316989).
Regarding claim 25. Lin discloses The method of claim 24, although Lin discloses the thick metal layer (70) formed by a plating [0031], Lin does not explicitly disclose electroless plating.
However, electroless plating is well known in the art with high level of generality for forming electrical layer. For example, Tsai discloses electrodeless plating [0071].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the Tsai’s electroless plating within Lin’s method for the purpose of providing enhanced uniform coating on complex shapes, excellent corrosion and wear resistance, high hardness, and good lubricity, all achieved chemically without external electricity.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over by Lin (US 20190006200) in view of Yoshioka (US 20190047250).
Regarding claim 27. Lin discloses The method of claim 1, But Lin does not explicitly disclose wherein the dielectric material is a photosensitive resin.
However, Lin discloses the filling material is resin based encapsulating material and photosensitive resin is well known in the art with high level of generality for forming electrical layer. For example, Yoshioka discloses photosensitive resin [0065].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Lin’s resin based filling material with Yoshioka’s photosensitive resin without departing from the scope of the claimed invention for the purpose of providing enhanced precision, faster processing, excellent electrical insulation, and better thermal management, enabling fine patterning for Redistribution Layers (RDLs) and void-free gap filling in advanced 3D packaging like FOPLP/FOWLP, boosting device density and performance while reducing warpage.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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