DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore:
a ring shape structure;
a plurality of ring shape structures; and
a plurality of ring shape structures that are in the first scribe line, as recited in claim 2
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Nowhere in the drawings is any feature with a ring shape shown; and figure 4, described as showing a ring shape structure, only shows one.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 4 recites “obtaining a plurality of pre-selected cutting sizes according to a wafer size and a size of the first device”. Applicant’s specification includes a sole example where the pre-selected cutting sizes, a wafer size, and a size of the first device are related to each other: “In an example, the pre-selected cutting size is in fact the cutting size that can satisfy the wafer size and the first device size.” (¶49). However, given the innumerable ways that a pre-selected cutting size may be obtained “according to a wafer size and a size of the first device”, the absence of any example calculations by which the pre-selected cutting sizes are subsequently obtained, and no elaboration on what is meant by the nonstandard description of “satisfy the wafer size and the first device size” which represents the sole instance of obtaining pre-selected cutting sizes according to a wafer size and a size of the first device, it is unknown where one of ordinary skill should even begin in order to obtain pre-selected cutting sizes as claimed. The courts have repeatedly held that "the specification must teach those skilled in the art how to make and use the full scope of the claimed invention without ‘undue experimentation’" or that any experimentation must be "reasonable". See Amgen Inc. et al. v. Sanofi et al., 598 U.S. 594, 2023 USPQ2d 602 (2023).
Claims 5-6 inherit this rejection for lack of enablement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4-6, and 8-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 2) As the ring shape structure identified in the drawings does not appear to have something identifiable as a ring shape, it is unclear what structure is required by reciting “ring shape structures” in the claim.
During examination, a ring shape structure was understood to be any portion of a material on a substrate.
(Re Claim 4) It is unclear what is required by “determining a maximum pre-selected cutting size...as a target cutting size that…retains the number of effective devices”. No number of effective devices that could be considered a starting point by which to determine if a number of effective devices is retained is clear from the specification or claims, and the provided graphs appear to show no maximal value at which the number of effective devices will stop decreasing.
During examination, the quoted limitation was understood to be just another way to state “a target cutting size that increases a number of effective devices after cutting”.
Claims 5-6 inherit this rejection for indefiniteness.
(Re Claim 5) Only a single target cutting size was recited in claim 4; reference to “the target cutting sizes” lacks antecedence.
During examination of this claim, “determining a maximum pre-selected cutting size among the plurality of pre-selected cutting sizes as a target cutting size” was read as “determining one or more maximum pre-selected cutting sizes among the plurality of pre-selected cutting sizes as one or more target cutting sizes”, as found in claim 4; “according to the target cutting size” was read as “according to the one or more target cutting sizes”; and “the target cutting sizes” was read as “the one or more target cutting sizes”.
Claim 6 inherits this rejection for lack of antecedence.
Furthermore, “the two first devices adjacent in the second direction” lacks antecedence.
During examination, this was read as “two first devices adjacent in the second direction”.
Claim 6 inherits this rejection for lack of antecedence.
Furthermore, it is unclear if “a size of the first scribe line in the first direction” and “a size of the second scribe line in the second direction” as recited in claim 5 are both references to the same sizes recited in claim 3, or these are new sizes.
During examination, “a size of the first scribe line in the first direction” and “a size of the second scribe line in the second direction” were read as “the size of the first scribe line in the first direction” and “the size of the second scribe line in the second direction” in claim 5.
Claim 6 inherits this rejection for indefiniteness.
(Re Claim 8) It is unclear if “a barrier structure extending in the second direction and located at a site in the first scribe line abutting the first device” requires only one first device to have a barrier structure so disposed by it in one particular first scribe line, or if each first device requires an abutting barrier structure in each first scribe line. A plurality of first devices and first scribe lines is claimed without clarity as to which is singled out by “the first device” or “the first scribe line”.
During examination, “a barrier structure…located at a site in the first scribe line abutting the first device” was read as “a barrier structure…located at a site in each first scribe line abutting each first device”
Claims 8-12 inherit this rejection for indefiniteness.
Rejection 1/2
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7-9, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumakawa et al. (US 2006/0163699).
(Re Claim 1) Kumakawa teaches a fabrication method of a semiconductor device, comprising: forming a semiconductor structure (Fig. 1 markup) in a wafer (1; Fig. 1, ¶68), comprising forming a first device (Fig. 1 markup) and a first scribe line (3; Fig. 2) abutting the first device in a first direction (left to right; Fig. 1) and extending in a second direction (top to bottom; Fig. 1), the first direction intersecting the second direction; and forming a barrier structure (as depicted in the Fig. 2 markup, with the full extent being from the bottom right corner of the first device to the top right corner of the first device) extending in the second direction at a site in the first scribe line abutting the first device.
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(Re Claim 2) Kumakawa teaches the method of claim 1, wherein forming the barrier structure extending in the second direction further comprises: forming a plurality of ring shape structures (each interlayer insulating film 5; Fig. 2, ¶70) extending in the second direction in the first scribe line (as seen in a plan view based on Fig. 1 and 2); and forming a plurality of grooves (space occupied by each element 8; Fig. 2 markup) arranged at intervals in the second direction in the ring shape structures, the grooves extending in the first direction (Fig. 2).
(Re Claim 7) Kumakawa teaches the method of claim 1, wherein the wafer comprises any one of an array wafer, a CMOS wafer, a carrier wafer and a device wafer (plurality of semiconductor devices 2; ¶68).
(Re Claim 8) Kumakawa teaches the semiconductor device, comprising: a wafer (1; Fig. 1, ¶68) including a plurality of semiconductor structures (Fig. 1 markup) each of which including a first device (the bottom left device 2 of each semiconductor structure; Fig. 1 markup) and a first scribe line (each scribe line 3 to the first device’s right; Fig. 1) abutting the first device in a first direction (left to right; Fig. 1 and 2) and extending in a second direction (top to bottom; Fig. 1 and 2), the first direction intersecting the second direction; and a barrier structure (the region in each semiconductor structure that is to the right of each first device, as identified in the Fig. 2 markup, where the extent is from the bottom right corner of the first device to the top right corner of the first device) extending in the second direction and located at a site in the first scribe line abutting the first device (Fig. 2 markup).
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(Re Claim 9) Kumakawa teaches the semiconductor device of claim 8, wherein the barrier structure comprises a plurality of grooves (corresponding to the space occupied by elements 8 within the barrier structure; Fig. 2 markup) arranged at intervals in the second direction and extending in the first direction (Fig. 1 and 2).
(Re Claim 12) Kumakawa teaches the semiconductor device of claim 8, wherein the wafer comprises any one of an array wafer, a CMOS wafer, a carrier wafer and a device wafer (plurality of semiconductor devices 2; ¶68).
Rejection 2/2
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2011/0241164) and Glenn et al. (US 6,399,463).
(Re Claim 1) Nakamura teaches a fabrication method of a semiconductor device, comprising: forming a semiconductor structure (Fig. 4A markup) in a wafer (61; Fig. 4A), comprising forming a first device (lower left Rd within the semiconductor structure) and identifying a region for a first scribe line (region Rsc located between the lower left Rd and lower right Rd in the semiconductor structure) abutting the first device in a first direction (left to right in a plan view; Fig. 4A) and extending in a second direction (top to bottom in a plan view; Fig. 4A), the first direction intersecting the second direction; and forming a barrier structure (where the extent of the barrier structure is from the lower right corner to the top right corner of the first device, as would be seen in a plan view as depicted in Fig. 5 markup; compare Fig. 1 and Fig. 5 for the location of each element 32) extending in the second direction at a site in the region identified for forming a first scribe line abutting the first device.
Nakamura does not teach forming a scribe line abutting the first device, and forming a barrier structure extending in the second direction at a site in the first scribe line abutting the first device.
Glenn teaches that it is typical to remove a dielectric layer (18; Fig. 1) to form scribe lines (14; Fig. 1) before singulation (col. 1 ln. 26-33 and col. 1 ln. 40-44).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form scribe lines coextensive with each region Rsc of Nakamura, as taught by Glenn, to allow for optical alignment for device singulation (Glenn: col. 1 ln. 40-44).
This results in Nakamura teaching forming a first scribe line (due to removal of layer 25 overlapping with region Rsc, that is between the lower left Rd and lower right Rd in the semiconductor structure, in the manner taught by Glenn) abutting the first device, and forming a barrier structure extending in the second direction at a site in the first scribe line abutting the first device (due to forming the first scribe line in the manner taught by Glenn).
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(Re Claim 2) Modified Nakamura teaches the method of claim 1, wherein forming the barrier structure extending in the second direction further comprises: forming a plurality of ring shape structures (the dielectric layers comprising element 13, excluding 25; Fig. 3 and 4A) extending in the second direction in the first scribe line (as seen in a plan view); and forming a plurality of grooves (space occupied by each element 32; Fig. 5 and 6) arranged at intervals in the second direction in the ring shape structures, the grooves extending in the first direction (Fig. 4A and 5).
(Re Claim 7) Modified Nakamura teaches the method of claim 1, wherein the wafer comprises any one of an array wafer, a CMOS wafer, a carrier wafer and a device wafer (devices Rd; ¶28).
(Re Claim 8) Nakamura teaches a semiconductor device, comprising: a wafer (61; Fig. 4A) including a plurality of semiconductor structures (Fig. 4A markup) each of which including a first device (lower left Rd as seen in a plan view; Fig. 4A) and a first scribe line region (Rsc located between the lower left Rd and lower right Rd of each semiconductor structure; Fig. 4A markup, and Fig. 5) abutting the first device in a first direction (left to right in a plan view; Fig. 4A and 5) and extending in a second direction (top to bottom in a plan view; Fig. 4A and 5), the first direction intersecting the second direction; and a barrier structure (where the extent of the barrier structure is from the lower right corner to the top right corner of the first device, as would be seen in a plan view as depicted in Fig. 5 markup; compare Fig. 1 and Fig. 5 for the location of each element 32) extending in the second direction and located at a site in the first scribe line region abutting the first device.
Nakamura does not explicitly teach forming a first scribe line.
Glenn teaches that it is typical to remove a dielectric layer (18; Fig. 1) to form scribe lines (14; Fig. 1) before singulation (col. 1 ln. 26-33 and col. 1 ln. 40-44).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form scribe lines coextensive with each region Rsc of Nakamura, as taught by Glenn, to allow for optical alignment for device singulation (Glenn: col. 1 ln. 40-44).
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This results in Nakamura teaching forming a first scribe line (due to removal of layer 25 overlapping with region Rsc, that is between the lower left Rd and lower right Rd in the semiconductor structure, in the manner taught by Glenn) abutting the first device, and forming a barrier structure extending in the second direction at a site in the first scribe line abutting the first device (due to forming the first scribe line in the manner taught by Glenn).
(Re Claim 9) Modified Nakamura teaches the semiconductor device of claim 8, wherein the barrier structure comprises a plurality of grooves (space occupied by each element 32; Fig. 5 and 6) arranged at intervals in the second direction and extending in the first direction (Fig. 4A and 5).
(Re Claim 12) Modified Nakamura teaches the semiconductor device of claim 8, wherein the wafer comprises any one of an array wafer, a CMOS wafer, a carrier wafer and a device wafer (devices Rd; ¶28).
Claims 3 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2011/0241164) and Glenn et al. (US 6,399,463) as applied to claims 1 and 9 above, and further in view of Choi et al. (US 2021/0175133), and Young (US 6,680,484).
(Re Claim 3) Modified Nakamura teaches the method of claim 1, wherein forming the semiconductor structure comprises forming a second scribe line (region Rsc located between the lower left Rd and upper left Rd in the semiconductor structure) abutting the first device in the second direction and extending in the first direction (Fig. 4A and 5).
Modified Nakamura has not been shown to explicitly teach a size of the first scribe line in the first direction is greater than a size of the second scribe line in the second direction.
Choi teaches forming a first scribe line (SL1; Fig. 24) and a second scribe line (SL2; Fig. 24) such that a size of the first scribe line in a first direction (left to right as seen in Fig. 24) is greater than a size of the second scribe line in a second direction (top to bottom as seen in Fig. 24; ¶85).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the first scribe line of modified Nakamura with a size in the first direction greater than a size of the second scribe line in the second direction, as taught by Choi, to reduce the amount of unnecessary space taken up by the second scribe line, increasing the number of dies produced (Young: col. 5 ln. 45-51).
(Re Claim 10) Modified Nakamura teaches the semiconductor device of claim 9, wherein the semiconductor structure further comprises a second scribe line (region Rsc located between the lower left Rd and upper left Rd in the semiconductor structure) abutting the first device in the second direction and extending in the first direction (Fig. 4A and 5)
Modified Nakamura has not been shown to explicitly teach a size of the first scribe line in the first direction is greater than a size of the second scribe line in the second direction.
Choi teaches forming a first scribe line (SL1; Fig. 24) and a second scribe line (SL2; Fig. 24) such that a size of the first scribe line in a first direction (left to right as seen in Fig. 24) is greater than a size of the second scribe line in a second direction (top to bottom as seen in Fig. 24; ¶85).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the first scribe line of modified Nakamura with a size in the first direction greater than a size of the second scribe line in the second direction, as taught by Choi, to reduce the amount of unnecessary space taken up by the second scribe line, increasing the number of dies produced (Young: col. 5 ln. 45-51).
(Re Claim 11) Modified Nakamura teaches the semiconductor device of claim 10, but has not been shown to explicitly teach a size of the barrier structure in the first direction is equal to a half of a difference between a first target size of the first scribe line in the first direction and a preset cutting size that is equal to a second target size of the second scribe line in the second direction.
However, Choi gives an overlapping range for possible sizes of a first scribe line (SL1) and a second scribe line (SL2; ¶¶35, 85).
Furthermore, Young teaches that it is understood by those in the art that a scribe line size should be large enough to accommodate test or alignment structures and small enough to maximize yield (Young: col. 5 ln. 45-51). As the scribe line size is a known result effective variable, it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the difference between the first and second scribe lines of modified Nakamura and arrive at the claimed size relationship between the barrier structure, and the difference between the first target size and a preset cutting size equal to a second target size of the second scribe line. With respect to the limitations of claim 11, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed size difference would have been obvious to one of ordinary skill in the art.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2011/0241164), Glenn et al. (US 6,399,463), Choi et al. (US 2021/0175133) and Young (US 6,680,484) as applied to claim 3 above, and further in view of Fürst et al. (US 2024/0282647) and Erck et al. (US 6,522,940).
(Re Claim 4) Modified Nakamura teaches the method of claim 3, but has not been shown to explicitly teach that before forming the semiconductor structure, the method further comprises: obtaining a plurality of pre-selected cutting sizes according to a wafer size and a size of the first device; determining a maximum pre-selected cutting size among the plurality of pre-selected cutting sizes as a target cutting size that increases a number of effective devices after cutting or retains the number of effective devices; and adjusting a semiconductor layout according to the target cutting size, the wafer size and the size of the first device.
Fürst teaches obtaining a plurality of pre-selected cutting sizes based on a size of the first device (“scribe line widths and cluster die size can be determined”; ¶33); determining a maximum pre-selected cutting size amount the plurality of pre-selected cutting sizes as a target cutting size that increases a number of effective devices after cutting or retains the number of effective devices (“with each iteration changing a selected design rule and reducing the smallest effective die area… In this manner, the most effective reticle 100 setup can be generated at the next process P10D that minimizes the wider scribe lines 150 and decreases effective die size to increase GDPW.” (¶33); “good dies per wafer (GDPW)” (¶2)); and adjusting a semiconductor layout (reticle; ¶33) according to the target cutting size and the size of the first device (¶34).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to perform the operations as shown by Fürst above before forming the semiconductor structure, to maximize the number of good dies formed on the wafer of modified Nakamura (Fürst: ¶33).
Erck teaches obtaining a plurality of pre-selected cutting sizes according to a wafer size and a size of a first device (Fig. 6; “Process 600 is performed for each combination of wafer size and scribe lane width (or production method)” (col. 10 ln. 7-10)); and adjusting a semiconductor layout according to a target cutting size, the wafer size, and the size of the first device (“build reticle layout”; Fig. 6).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to obtain pre-selected cutting sizes according to a wafer size and a size of the first device as taught by Erck, before forming the semiconductor structure of modified Nakamura, as this allows for a maximum number of effective devices on an entire wafer for each of the pre-selected cutting sizes to be determined. As the pre-selected cutting sizes of modified Nakamura are obtained according to a wafer size, the semiconductor layout will also be adjusted according to the wafer size due to adjustment according to the target cutting size.
(Re Claim 5) Modified Nakamura teaches the method of claim 4, but has not been shown to explicitly teach the target cutting sizes comprise a first target size in the first direction and a second target size in the second direction, and the adjusting the semiconductor layout comprises: setting a size of the first scribe line in the first direction according to the first target size and setting a size of the second scribe line in the second direction according to the second target size; and setting arrangement positions of a plurality of the first devices according to the target cutting size, the wafer size and the size of the first devices, wherein two first devices adjacent in the first direction are isolated by the first scribe line and the two first devices adjacent in the second direction are isolated by the second scribe line.
Fürst teaches determining a maximum pre-selected cutting size amount the plurality of pre-selected cutting sizes as a target cutting size that increases a number of effective devices after cutting or retains the number of effective devices (¶33).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to determine a maximum pre-selected cutting size among the plurality of pre-selected cutting sizes that ultimately determines both a first target size and a second target size respectively corresponding to the size of the first scribe line in the first direction and the size of the second scribe line in the second direction, in the manner for finding a target size as taught by Fürst (Fürst: ¶33), as the number of effective devices after cutting is dependent on both scribe line sizes (Choi: Fig. 24; Young: col. 5 ln. 45-51; see the rejection of claim 3 above).
Fürst teaches setting arrangement positions of a plurality of first devices (216; Fig. 5, ¶38) according to a target cutting size (as determined by what maximizes the number of effective devices; ¶33) and the size of the first devices (Fig. 6), wherein two first devices adjacent in a first direction (left to right; Fig. 5) are isolated by a first scribe line (element 240 going from top to bottom; Fig. 5) and two first devices adjacent in a second direction (top to bottom; Fig. 5) are isolated by a second scribe line (element 240 going from left to right; Fig. 5).
A PHOSITA would find it obvious to set the arrangement positions of the first devices of modified Nakamura according to the target cutting sizes as determined according to Fürst, in order to fabricate devices on a wafer organized to produce a maximum number of effective devices under certain constraints (Fürst: ¶33).
Erck adjusting a semiconductor layout according to a target cutting size, the wafer size, and the size of the first device (“build reticle layout”; Fig. 6).
A PHOSITA would also find it obvious to set the arrangement positions of the first devices of modified Nakamura according to the wafer size, as taught by Erck, as this allows for the device yield of the entire wafer to be maximized (Erck: col. 10 ln. 7-15).
(Re Claim 6) Modified Nakamura teaches the method of claim 5, but has not been explicitly shown to teach a size of the barrier structure in the first direction is equal to a half of a difference between the first target size of the first scribe line in the first direction and a preset cutting size that is equal to the second target size of the second scribe line in the second direction.
However, Choi gives an overlapping range for possible sizes of a first scribe line (SL1) and a second scribe line (SL2; ¶¶35, 85).
Furthermore, Young teaches that it is understood by those in the art that a scribe line size should be large enough to accommodate test or alignment structures and small enough to maximize yield (Young: col. 5 ln. 45-51). As the scribe line size is a known result effective variable, it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the difference between the first and second scribe lines of modified Nakamura and arrive at the claimed size relationship between the barrier structure, and the difference between the first target size and a preset cutting size equal to a second target size of the second scribe line. With respect to the limitations of claim 6, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed size difference would have been obvious to one of ordinary skill in the art.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US 2021/0265308) and Nakamura (US 2011/0241164).
(Re Claim 13) Norman teaches a memory system, comprising: memory (702; Fig. 7); and
a controller (704; Fig. 7) that is coupled to the memory (Fig. 7) and configured to control the memory to store data (¶¶46-48).
Norman has not been shown to explicitly teach a memory system comprising:
a three-dimensional memory, the three-dimensional memory comprising a semiconductor device comprising: a wafer including a plurality of semiconductor structures each of which including a first device and a first scribe line abutting the first device in a first direction and extending in a second direction, the first direction intersecting the second direction; and a barrier structure extending in the second direction and located at a site in the first scribe line abutting the first device, a controller that is coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.
Norman teaches forming memory (500; Fig. 5), the memory comprising a semiconductor device comprising:
a wafer (501; Fig. 5) including a plurality of semiconductor structures (502a+scribe area along the right of 502a and 502c+scribe area along the right of 502c; Fig. 5) each of which includes a first device (502a and 502c respectively; Fig. 5) and a first scribe line (the scribe areas as defined for the semiconductor structures, respectively; Fig. 5) abutting the first device in a first direction (left to right; Fig. 5) and extending in a second direction (top to bottom; Fig. 5), the first direction intersecting the second direction (Fig. 5).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the memory shown in the embodiment of Fig. 5 for the memory shown in the embodiment of Fig. 7 of Norman, as this allows for increased memory capacity while maintaining short signal line length.
Norman also teaches that memory may be a three-dimensional memory (QV memory may be 3D QVM; ¶24).
A PHOSITA would find it obvious to form the memory as three-dimensional memory as doing so results in forming high-capacity memory (¶7).
This then results in the controller coupled to the three-dimensional memory and configured to control the three-dimensional memory to store date.
Nakamura teaches forming a barrier structure (Fig. 5 markup) extending in a second direction (top to bottom, with the full extent of the barrier structure being from the top right corner of a first device Rd located at the bottom left of Fig. 5 to the bottom right corner of the first device Rd; Fig. 5) and located at a site (coextensive with the barrier structure as defined) in a first scribe line region (Rsc; Fig. 5) abutting a first device (Rd; Fig. 5).
A PHOSITA would find it obvious to form a barrier structure as taught by Nakamura in the first scribe line of Norman to prevent peeling of device layers during singulation (Nakamura: ¶29).
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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