Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 03/17/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a composite structure located on the conductive layer…the composite structures comprising"(emphasis examiner’s) in lines 3-5. There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, examiner will understand the claim to mean “a plurality of composite structures located on the conductive layer and stacked in a direction perpendicular to a plane in which the conductive layer is located, each composite structure comprising:”
Claims 2-10 are rejected under 35 U.S.C. 112(b) as being dependent upon a claim rejected under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US20110237004A1, hereinafter Lee).
Regarding claim 1, Lee discloses a semiconductor device, comprising:
a conductive layer comprising a first pad (See below annotated fig. 4 substrate 31 with plurality of connection terminals 45 which par. 42 describes as “sometimes referred to as ball pad[s]”);
a composite structure located on the conductive layer and stacked in a direction perpendicular to a plane in which the conductive layer is located, the composite structures comprising:
a chip (See below annotated fig. 4 chips 11);
an insulating layer surrounding the chip (See below annotated fig. 4 resin encapsulant 41 surrounds chips 11); and
a second pad connected with the chip and over the insulating layer (See below annotated fig. 4 chip pads 12), the second pad of the composite structure being at different locations in a first direction, and the first direction being perpendicular to a thickness direction of the composite structure(See below annotated fig. 4 chip pads 12 in different locations in a direction perpendicular to the thickness direction); and
a conductive post located in the insulating layer of the composite structure, the conductive post connecting the first pad and the second pad (See below annotated fig. 4 connection vias 19 located in resin encapsulant 41 and connects connection terminals 45 with chip pads 12).
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Regarding claim 2, Lee discloses the semiconductor device of claim 1,
wherein a first conductive post extends in the direction perpendicular to the plane in which the conductive layer is located, and the first conductive post and a second conductive post are disposed parallel to each other (See above annotated fig. 4 leftmost connection via 19 extends in a direction perpendicular to the plane of substrate 31 and rightmost connection via 19 which extends in a direction parallel to leftmost connection via 19).
Regarding claim 6, Lee discloses the semiconductor device of claim 1,
wherein in the at least one of the composite structures, a number of the second pads are electrically connected with the chip and distances between the chip and the number of the second pads connected therewith are equal (See above annotate fig. 4 chips 11 have a plurality of chip pads 12 disposed on them with equal distances between them).
Regarding claim 7, Lee discloses the semiconductor device of claim 1,
wherein in at least one of the composite structures, a number of second pads are electrically connected with the chip and a plurality of the second pads are located on at least two sides of the chip electrically connected therewith (See above annotate fig. 4 chips 11 have a plurality of chip pads 12 disposed on them on two sides of the chip).
Regarding claim 8, Lee discloses the semiconductor device of claim 1,
wherein the insulating layer comprises an organic material (See above annotated fig. 4, resin encapsulant 41 is an organic material).
Regarding claim 9, Lee discloses the semiconductor device of claim 1,
wherein the composite structure further comprises a connection wiring layer, the connection wiring layer is located on a surface of a side of the chip close to the conductive layer, and
the connection wiring layer comprises connection wires and second pads, and the chip is electrically connected with the second pads via the connection wires (See above annotated fig. 4 connection via 19 has extension portion under chips 11 and connects to chip pads 12).
Regarding claim 10, Lee discloses the semiconductor device of claim 1,
wherein the composite structure further comprises a dielectric layer covering the chip and the insulating layer (Fig. 3 passivation layer 13 covers chip 11 and resin encapsulant 41), and
the conductive posts penetrate through the insulating layer and the dielectric layer over respective second pads and are electrically connected with second pads (See above annotated fig. 4 connection vias 19 penetrate through resin encapsulant 41 and passivation layer 13 and are electrically connected to chip pads 12).
Regarding claim 11, Lee discloses a chip package structure, comprising:
a packaging substrate (Par. 50 teaches “solder balls 45 may be formed on or applied to the lower surface of vias 33 on the lower surface of the test wafer 30, which corresponds to the common substrate 31 of FIG. 3, to provide external connections for mounting and electrically connecting the chip stack package on a PCB or other substrate” and so Lee teaches an additional substrate mounted on top of the above annotated fig. 4);
a package housing (Par. 6 teaches “[a]n encapsulating body 550 is then formed to surround and protect the chips 511 and 513, the wires 541 and 543, and at least a portion of the top surface of the substrate 520 from the environment”); and
a semiconductor device comprising:
a conductive layer comprising a first pad (See above annotated fig. 4 substrate 31 with plurality of connection terminals 45 which par. 42 describes as “sometimes referred to as ball pad[s]”);
a composite structure located on the conductive layer and stacked in a direction perpendicular to a plane in which the conductive layer is located, the composite structure comprising:
a chip (See above annotated fig. 4 chips 11);
an insulating layer surrounding the chip (See above annotated fig. 4 resin encapsulant 41 surrounds chips 11); and
a second pad electrically connected with the chip and over the insulating layer (See above annotated fig. 4 chip pads 12), the second pad of the composite structure being at different locations in a first direction, and the first direction being perpendicular to a thickness direction of the composite structure (See below annotated fig. 4 chip pads 12 in different locations in a direction perpendicular to the thickness direction); and
a conductive post located in the insulating layer of the composite structure, the conductive post connecting the second pad and the first pad (See above annotated fig. 4 connection vias 19 located in resin encapsulant 41 and connects connection terminals 45 with chip pads 12),
wherein the packaging substrate is attached to a side of the conductive layer away from the composite structure in the semiconductor device, and the package housing is snap- fitted on the composite structure and attached to the packaging substrate (The above taught packaging substrate is an external connection and so it is on a side of substrate 31 away from chips 11 and par. 6 teaches “[a]n encapsulating body 550 is then formed to surround and protect the chips 511 and 513, the wires 541 and 543, and at least a portion of the top surface of the substrate 520 from the environment”).
Allowable Subject Matter
Claims 3-5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3 and its dependent claims. The closest prior art (US20110237004A1, US20130147063A1, US20200303361A1) teaches the semiconductor device of claim 1,
wherein the composite structure closest to the conductive layer is a first composite structure.
However, the closest prior art does not teach in combination with the other claimed elements
in the direction perpendicular to the plane in which the conductive layer is located and away from the conductive layer, a distance between a first conductive post and a second conductive post connected with the second pad on a same side of the chip in the composite structure and the chip of the first composite structure increases gradually.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Examiner notes that while there are embodiments within the prior art, see above Lee annotated fig. 4, that teach a composite structure with a plurality of conductive posts on opposite sides of a chip, examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments such that in the direction perpendicular to the plane in which the conductive layer is located and away from the conductive layer, a distance between a first conductive post and a second conductive post connected with the second pad on a same side of the chip in the composite structure and the chip of the first composite structure increases gradually in addition with the other limitations of the independent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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