Prosecution Insights
Last updated: July 17, 2026
Application No. 18/528,328

SUBSTRATE TREATING APPARATUS AND SEMICONDUCTOR MANUFACTURING EQUIPMENT INCLUDING THE SAME

Non-Final OA §103
Filed
Dec 04, 2023
Priority
Dec 20, 2022 — RE 10-2022-0179760
Examiner
ASFAW, MESFIN T
Art Unit
3652
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Semes Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
808 granted / 976 resolved
+30.8% vs TC avg
Moderate +14% lift
Without
With
+14.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
24 currently pending
Career history
1006
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
78.0%
+38.0% vs TC avg
§102
16.8%
-23.2% vs TC avg
§112
0.2%
-39.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 976 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. [US 20200081347 A1, hereafter Choi] in view of Davis et al. [US 20100009470 A1, hereafter Davis]. As per Claim 1, Choi teaches Semiconductor manufacturing equipment (See fig. 3) comprising: load ports 22 where containers (substrates W from carriers 10) loaded with a plurality of substrates are mounted (Para 43); a buffer module (a buffer chamber 3800) temporarily storing the substrates (Para 48); an index module (index module 20) transferring the substrates between the load ports and the buffer module (Para 42); a plurality of process chambers treating the substrates (Para 48); a transfer module (transfer unit 3420) transferring the substrates between the buffer module and the process chambers (Para 50). Choi do not explicitly teach a substrate treating apparatus performing critical dimension (CD) measurement and calibration on the substrates, wherein the substrate treating apparatus is disposed adjacent to the process chambers. Davis teaches a metrology (IM) chamber integrated into a processing platform, such as the IM chamber 425 of the multi-chambered processing platform 400. While depicted as a dedicated module coupled directly coupled to a transfer module 401, the IM chamber 425 may also be integrated into one or more of the process chambers 402, 405, 410, 415 or 420 (See fig. 4, Para 27). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a metrology chamber as disclosed by Davis in the manufacturing equipment of Choi in order to adaptively adjusting process parameters more accurately. As per Claims 2, 4 and 5, Choi in view of Davis teaches the semiconductor manufacturing equipment of claim 1, wherein the process chambers are divided and arranged on both sides of the transfer module, and the substrate treating apparatus is disposed on one of the two sides of the transfer module (See Choi fig. 3 in view of Davis fig. 4). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a metrology chamber as disclosed by Davis in the manufacturing equipment of Choi in order to adaptively adjusting process parameters more accurately. As per Claim 3, Choi in view of Davis teaches the semiconductor manufacturing equipment of claim 2. Choi further disclosed wherein process chambers disposed on one side of the transfer module are process chambers that perform heat treatment (heat treatment chamber 3200) on the substrates, and process chambers disposed on the other side of the transfer module are process chambers that perform a development process (developing chamber 3600) on the substrates (See fig. 3, Para 49). As per Claim 6, Choi in view of Davis teaches the semiconductor manufacturing equipment of claim 1. Davis further disclosed wherein the substrate treating apparatus includes an inspection module measuring a CD of the substrates, a control module determining whether a linewidth of patterns formed on the substrates meets a reference value based on results of the measurement of the CD of the substrates, and a calibration module performing the CD calibration on the substrates if the linewidth of the patterns formed on the substrates does not meet the reference value (See fig. 4, Para 27 and 32-33). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a metrology chamber as disclosed by Davis in the manufacturing equipment of Choi in order to adaptively adjusting process parameters more accurately. Claim(s) 7-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Davis, and further in view of deVilliers et al. [US 20170330806 A1, hereafter deVilliers]. As per Claims 7-11, Choi in view of Davis teaches the semiconductor manufacturing equipment of claim 6. Choi in view of Davis do not explicitly teach wherein the control module divides each of the substrates into a plurality of areas and determines whether the linewidth of the patterns meets the reference value for each of the plurality of areas. deVilliers teaches location-specific dose delivery method, dose is delivered via rotating and translating the wafer under a fixed light source. The light source, for example, could be a single controllable source (e.g., a 300+mm size bulb) or a series of controllable, independent zones (e.g., along the long axis of the light source). Similarly, the wafer could be fixed, and the light could rotate and translate over the wafer. Such a hardware concept allows for many pathways to alter the dose signature delivered within-wafer (WIW) to alter the final WIW CD alteration signature (Para 14 and 31). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a critical dimension control method as disclosed by deVilliers in order to maximize the amount of CD alteration and an alternative flow for control/correction. As per Claims 12-16, Choi in view of Davis teaches the semiconductor manufacturing equipment of claim 1. Choi in view of Davis do not explicitly teach wherein the process chambers include a process chamber that performs a post exposure bake (PEB) process, and the substrate treating apparatus performs the CD measurement and calibration on substrates that have undergone the PEB process. deVilliers teaches wherein the process chambers include a process chamber that performs a post exposure bake (PEB) process, and the substrate treating apparatus performs the CD measurement and calibration on substrates that have undergone the PEB process (Para 14). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a critical dimension control method as disclosed by deVilliers in order to maximize the amount of CD alteration and an alternative flow for control/correction. As per Claim 17, Choi teaches a substrate treating apparatus comprising: wherein the substrate treating apparatus is disposed adjacent to a plurality of process chambers that treat the substrates, within semiconductor manufacturing equipment (See fig. 3, Para 12). Choi does not explicitly teach an inspection module measuring a critical dimension (CD) of substrates; a control module determining whether a linewidth of patterns formed on the substrates meets a reference value based on results of the measurement of the CD of the substrates; and a calibration module performing CD calibration on the substrates if the linewidth of the patterns formed on the substrates does not meet the reference value, wherein the substrate treating apparatus is disposed adjacent to a plurality of process chambers that treat the substrates, within semiconductor manufacturing equipment. Davis teaches an inspection module measuring a critical dimension (CD) of substrates’ wherein the substrate treating apparatus is disposed adjacent to a plurality of process chambers that treat the substrates, within semiconductor manufacturing equipment (See fig. 4, Para 35). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a metrology chamber as disclosed by Davis in the manufacturing equipment of Choi in order to adaptively adjusting process parameters more accurately. Choi in view of Davis do not explicitly teach a control module determining whether a linewidth of patterns formed on the substrates meets a reference value based on results of the measurement of the CD of the substrates; and a calibration module performing CD calibration on the substrates if the linewidth of the patterns formed on the substrates does not meet the reference value. deVilliers teaches location-specific dose delivery method, dose is delivered via rotating and translating the wafer under a fixed light source. The light source, for example, could be a single controllable source (e.g., a 300+mm size bulb) or a series of controllable, independent zones (e.g., along the long axis of the light source). Similarly, the wafer could be fixed, and the light could rotate and translate over the wafer. Such a hardware concept allows for many pathways to alter the dose signature delivered within-wafer (WIW) to alter the final WIW CD alteration signature (Para 14 and 31). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a critical dimension control method as disclosed by deVilliers in order to maximize the amount of CD alteration and an alternative flow for control/correction. As per Claim 18, Choi in view of Davis and deVilliers teaches the substrate treating apparatus of claim 17. Choi further disclosed wherein the process chambers are divided and arranged on both sides of a transfer module equipped with a robot for transferring the substrates, process chambers disposed on one side of the transfer module are process chambers that perform heat treatment on the substrates, process chambers disposed on the other side of the transfer module are process chambers that perform a development process on the substrates, and the substrate treating apparatus is disposed adjacent to a process chamber that performs a hard bake process, among the process chambers that perform heat treatment on the substrates (See fig. 3). As per Claim 19, Choi in view of Davis and deVilliers teaches the substrate treating apparatus of claim 17. deVilliers further disclosed wherein the substrate treating apparatus performs the CD measurement and calibration on at least one substrate that has gone through a hard bake process, a post exposure bake (PEB) process, or an exposure process or applies heat to a substrate to be subject to the PEB process, using a laser light source (Para 14 and 31). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a critical dimension control method as disclosed by deVilliers in order to maximize the amount of CD alteration and an alternative flow for control/correction. As per Claim 20, Choi teaches Semiconductor manufacturing equipment (See fig. 3) comprising: load ports 22 where containers (substrates W from carriers 10) loaded with a plurality of substrates are mounted (Para 42); a buffer module (a buffer chamber 3800) temporarily storing the substrates (Para 48); an index module (index module 20) transferring the substrates between the load ports and the buffer module (Para 42); a plurality of process chambers treating the substrates (Para 50); a transfer module (transfer unit 3420) transferring the substrates between the buffer module and the process chambers (Para 50)’ wherein the process chambers are divided and arranged on both sides of the transfer module, which is equipped with a robot for transferring the substrates (See fig. 3). Choi do not explicitly teach a substrate treating apparatus performing critical dimension (CD) measurement and calibration on the substrates, process chambers disposed on one side of the transfer module are process chambers that perform heat treatment on the substrates, process chambers disposed on the other side of the transfer module are process chambers that perform a development process on the substrates, the substrate treating apparatus is disposed adjacent to a process chamber that performs a hard bake process, among the process chambers that perform heat treatment on the substrates, the substrate treating apparatus includes an inspection module measuring CD of the substrates. Davis teaches a metrology (IM) chamber integrated into a processing platform, such as the IM chamber 425 of the multi-chambered processing platform 400. While depicted as a dedicated module coupled directly coupled to a transfer module 401, the IM chamber 425 may also be integrated into one or more of the process chambers 402, 405, 410, 415 or 420 (See fig. 4, Para 27). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a metrology chamber as disclosed by Davis in the manufacturing equipment of Choi in order to adaptively adjusting process parameters more accurately. choi in view of Davis do not explicitly teach a control module determining whether a linewidth of patterns formed on the substrates meets a reference value based on results of the measurement of the CD of the substrates, and a calibration module performing the CD calibration on selected areas of the substrates based on results of the determination, and the substrate treating apparatus performs the CD measurement and calibration on at least one substrate that has gone through a hard bake process, a post exposure bake (PEB) process, or an exposure process or applies heat to a substrate to be subject to the PEB process, using a laser light source. deVilliers teaches location-specific dose delivery method, dose is delivered via rotating and translating the wafer under a fixed light source. The light source, for example, could be a single controllable source (e.g., a 300+mm size bulb) or a series of controllable, independent zones (e.g., along the long axis of the light source). Similarly, the wafer could be fixed, and the light could rotate and translate over the wafer. Such a hardware concept allows for many pathways to alter the dose signature delivered within-wafer (WIW) to alter the final WIW CD alteration signature (Para 14 and 31). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate a critical dimension control method as disclosed by deVilliers in order to maximize the amount of CD alteration and an alternative flow for control/correction. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MESFIN ASFAW whose telephone number is (571)270-5247. The examiner can normally be reached Monday - Friday 8 am - 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toan Ton can be reached at 571-272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MESFIN T ASFAW/ Primary Examiner, Art Unit 2882
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Prosecution Timeline

Dec 04, 2023
Application Filed
Jun 05, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
97%
With Interview (+14.1%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 976 resolved cases by this examiner. Grant probability derived from career allowance rate.

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