DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed January 7, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 6, 12, 14, 17, and 20 drawn to non-elected invention have been withdrawn. Claims 1, 3, 7, 10, 16, and 18 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7-11, 13, 15-16, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0343449 A1 to Aaron Lee, et al. (hereafter Lee) in view of US 2022/0180948 A1 to Sarath Puthenthermadam, et al. (hereafter Puthenthermadam).
Regarding Independent Claim 1, Lee discloses a method, comprising:
determining that a first group of word line segments (Disclosing a first group of word lines: Lee, ¶[0050]) associated with a block of memory cells (Associated with an open block: Lee, ¶[0050]) are in a programmed state (Defining an ‘open block’ as a partially programmed block with both programmed and erased memory cells: Lee, ¶[0040]);
determining that a second group of word line segments (Disclosing a second group of word lines: Lee, ¶[0050]) associated with the block of memory cells are in an unprogrammed state (The open block containing both programmed and unprogrammed/erased cells: Lee, ¶[0040]);
Lee discloses determining which wordlines in a block contain programmed memory cells and which contain unprogrammed cells allows for the use of differing erase verification voltages (Lee, ¶[0051]), which it refers to as erase verify bias voltages (Lee, ¶[0051]). The specification for the instant application, however, discusses ‘debiasing voltages’ exclusively in terms of the main erase operation, not during the verification step (Detailed Description, ¶[0020]). Although broadest reasonable interpretation does not demand such a distinction, in the interest of compact prosecution, ‘debiasing voltage’ will be interpreted as being applied along with the erase voltage pulses.
Under that interpretation, Puthenthermadam discloses an erase operation wherein:
applying, during an erase operation of the block of memory cells (The first debiasing voltage being used during an erase operation: Puthenthermadam, ¶[0114]; See Also, an erase operation comprising an erase pulse and an erase-verification step: Puthenthermadam, ¶[0099] and Figure 8B), a first debiasing voltage (Disclosing a first erase bias voltage: Puthenthermadam, ¶[0062]) to the first group of word line segments (The first erase bias voltage applied to the first group of word line segments: Puthenthermadam, ¶[0114])
based on the determination that the first group of word line segments are in the programmed state (The first erase bias voltage used because the cells are in a programmed state: Puthenthermadam, ¶[0114]); and
applying, during the erase operation (The second debiasing voltage being used during an erase operation: Puthenthermadam, ¶[0114]), a second debiasing voltage (Disclosing a second erase bias inhibit voltage: Puthenthermadam, ¶[0114]) to the second group of word line segments
based on the determination that the second group of word line segments are in the unprogrammed state (Applying a erase bias inhibit voltage to the second group of wordlines in the erased/unprogrammed state: Puthenthermadam, ¶[0114]).
Puthenthermadam teaches the application of different bias voltages to word lines can affect the erase speed of the programmed cells, as well as affecting erase disturbances on the unselected word lines (Puthenthermadam, ¶[0047]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the variable erase biases of Puthenthermadam with the programmed/unprogrammed memory cell determination of Lee, with a reasonable expectation of success. Both inventions are well known in the field of sub-block level erasure and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2 and the substantially similar limitations of Claims 9 and 19, Puthenthermadam discloses the method of claim 1, wherein
the second debiasing voltage is larger than the first debiasing voltage (The second debiasing voltage UERA_SBM_SB1 being larger than the first debiasing voltage VERA_WL_1: Puthenthermadam, ¶[0116])
relative to a voltage applied to a pillar area associated with the block of memory cells (The comparison of voltages being relative to the applied VERA: Puthenthermadam, ¶[0115]).
Regarding Claim 3 and the substantially similar limitations of Claim 10 and 18, Puthenthermadam discloses the method of claim 1, further comprising:
applying the first debiasing voltage to the first group of word line segments (Applying the first debiasing voltage to the first group word line segments: Puthenthermadam, ¶[0114]) as part of performance of the operation to erase data written to memory cells coupled to the first group of word lines (The first debiasing voltage being applied to encourage the erasing of memory cells connected with the selected word line: Puthenthermadam, ¶[0114]); and
applying the second debiasing voltage to the second group of word line segments (Applying the second debiasing voltage to the second group word line segments: Puthenthermadam, ¶[0114]) as part of performance of the operation to erase data written to memory cells coupled to the second group of word lines (Applying the second debiasing voltage during the erase operation: Puthenthermadam, ¶[0114]).
Regarding Claim 4, Lee discloses the method of claim 1, further comprising
determining that the block of memory cells is partially programmed (Disclosing an open block consisting of programmed and unprogrammed word lines: Lee, ¶[0050]) as part of
determining that the first group of word line segments are in the programmed state (Wherein the first set of word lines are in a programmed state: Lee, ¶[0050]) and
determining that the second group of word line segments are in the unprogrammed state (Wherein the second group of word lines are in an unprogrammed state: Lee, ¶[0050]).
Regarding Claim 5, Lee discloses the method of claim 1, further comprising
determining, as part of determining that the first group of word line segments are in the programmed state or determining that the second group of word line segments are in the unprogrammed state, or both (Identifying which word lines are programmed and which are unprogrammed: Lee, ¶[0050]),
by determining a last programmed word line associated with the block of memory cells (Memory controller mapping unprogrammed cells by identification of the last programmed word line: Lee, ¶[0050]).
Regarding Independent Claim 7, Lee discloses an apparatus, comprising:
a block of memory cells (Memory cells in a block: Lee, ¶[0016]) coupled to a plurality of word lines (Coupled to word lines: Lee, ¶[0016]); and
a processor (Controller 102, which may include a processor: Lee, ¶[0021]) coupled to the block of memory cells (Controller 102 coupled to the block of memory cells: Lee, Figure 1A), wherein the processor is configured to:
assign a first status to a first group of word lines among the plurality of word lines (Disclosing a first group of word lines: Lee, ¶[0050]);
assign a second status to a second group of word lines among the plurality of word lines (Disclosing a second group of word lines: Lee, ¶[0050]);
Lee discloses determining which wordlines in a block contain programmed memory cells and which contain unprogrammed cells allows for the use of differing erase verification voltages (Lee, ¶[0051]), which it refers to as erase verify bias voltages (Lee, ¶[0051]). The specification for the instant application, however, discusses ‘debiasing voltages’ exclusively in terms of the main erase operation, not during the verification step (Detailed Description, ¶[0020]). Although broadest reasonable interpretation does not demand such a distinction, in the interest of compact prosecution, ‘debiasing voltage’ will be interpreted as being applied along with the erase voltage pulses.
Under that interpretation, Puthenthermadam discloses an erase operation wherein:
apply, during an erase operation of the block of memory cells (The first debiasing voltage being used during an erase operation: Puthenthermadam, ¶[0114]; See Also, an erase operation comprising an erase pulse and an erase-verification step: Puthenthermadam, ¶[0099] and Figure 8B), a first debiasing voltage (Disclosing a first erase bias voltage: Puthenthermadam, ¶[0062]) to the first group of word lines based on the first group of word lines being assigned the first status (The first erase bias voltage applied to the first group of word line segments: Puthenthermadam, ¶[0114]); and
apply, during the erase operation (The second debiasing voltage being used during an erase operation: Puthenthermadam, ¶[0114]), a second debiasing voltage (Disclosing a second erase bias inhibit voltage: Puthenthermadam, ¶[0114]) to the second group of word lines based on the second group of word lines being assigned the second status (Applying a erase bias inhibit voltage to the second group of wordlines in the erased/unprogrammed state: Puthenthermadam, ¶[0114]).
Puthenthermadam teaches the application of different bias voltages to word lines can affect the erase speed of the programmed cells, as well as affecting erase disturbances on the unselected word lines (Puthenthermadam, ¶[0047]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the variable erase biases of Puthenthermadam with the programmed/unprogrammed memory cell determination of Lee, with a reasonable expectation of success. Both inventions are well known in the field of sub-block level erasure and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 8, Puthenthermadam discloses the apparatus of claim 7, wherein the processor is configured to:
assign the first status to the first group of word lines when the first group of word lines are coupled to memory cells that are in a programmed state (The first erase bias voltage used because the cells are in a programmed state: Puthenthermadam, ¶[0114]); and
assign the second status to the second group of word lines when the second group of word lines are coupled to memory cells that are in an unprogrammed state (The second erase bias voltage used because the cells are in an unprogrammed state: Puthenthermadam, ¶[0114]).
Regarding Claim 11, Lee discloses the apparatus of claim 7, wherein the processor is configured to:
determine a last programmed word line associated with the block of memory cells (Memory controller mapping unprogrammed cells by identification of the last programmed word line: Lee, ¶[0050]); and
assign the first status to the first group of word lines or (Identifying which word lines are programmed: Lee, ¶[0050])
assign the second status to the second group of word lines (Identifying which word lines are unprogrammed: Lee, ¶[0050])
based on the determined last programmed word line associated with the block of memory cells (Based on the last programmed word line: Lee, ¶[0050]).
Regarding Claim 13, Lee discloses the apparatus of claim 7, wherein
the processor is configured to determine that the block of memory cells is experiencing a partial block condition (Describing an open block having both programmed and unprogrammed memory cells: Lee, ¶[0040]) prior to:
assignment of the first status, the second status, or both (Lee does not expressly describe assigning the first or second status, but does teach identifying the regions, therefore teaching both A. the prior unidentified regions and B. the subsequent determination: Lee, ¶[0050]); or
application of the first debiasing voltage or the second debiasing voltage, or both (Identifying the boundary between programmed and unprogrammed word lines prior to applying bias voltages: Lee, ¶[0050]).
Regarding Claim 15, Lee discloses the apparatus of claim 7, wherein
the block of memory cells and the processor are resident on a solid state drive (The memory cells and processor as part of a solid-state drive: Lee, ¶[0024]).
Regarding Independent Claim 16, Lee discloses a non-transitory machine-readable storage medium (Disclosing a non-volatile memory system: Lee, ¶[0002]) comprising instructions (Instructions are inherent in a processer) that, when executed by a processing device (Controller 102, which may include a processor: Lee, ¶[0021]), cause the processing device to:
determine a last programmed word line associated with a plurality of word lines of a block of memory cells (Memory controller mapping unprogrammed cells by identification of the last programmed word line: Lee, ¶[0050]);
assign a first status to a first group of word lines among the plurality of word lines (Disclosing a first group of word lines: Lee, ¶[0050]),
wherein the first group of word lines includes the last programmed word line and word lines and programmed word lines adjacent to the last programmed word line (The first group including word lines WL1 through WLn-1, comprising the programmed word lines: Lee, ¶[0050]);
assign a second status to a second group of word lines among the plurality of word lines,
wherein the second group of word lines includes unprogrammed word lines adjacent to the last programmed word line (The second group including the remaining word lines, including WLn where WLn is the first unprogrammed word line, comprising the unprogrammed word lines: Lee, ¶[0050]);
Lee discloses determining which wordlines in a block contain programmed memory cells and which contain unprogrammed cells allows for the use of differing erase verification voltages (Lee, ¶[0051]), which it refers to as erase verify bias voltages (Lee, ¶[0051]). The specification for the instant application, however, discusses ‘debiasing voltages’ exclusively in terms of the main erase operation, not during the verification step (Detailed Description, ¶[0020]). Although broadest reasonable interpretation does not demand such a distinction, in the interest of compact prosecution, ‘debiasing voltage’ will be interpreted as being applied along with the erase voltage pulses.
Under that interpretation, Puthenthermadam discloses an erase operation wherein:
apply, during an erase operation of the block of memory cells (The first debiasing voltage being used during an erase operation: Puthenthermadam, ¶[0114]; See Also, an erase operation comprising an erase pulse and an erase-verification step: Puthenthermadam, ¶[0099] and Figure 8B), a first debiasing voltage (Disclosing a first erase bias voltage: Puthenthermadam, ¶[0062]) to the first group of word lines based on the first group of word lines being assigned the first status (The first erase bias voltage applied to the first group of word line segments: Puthenthermadam, ¶[0114]); and
apply, during the erase operation (The second debiasing voltage being used during an erase operation: Puthenthermadam, ¶[0114]), a second debiasing voltage (Disclosing a second erase bias inhibit voltage: Puthenthermadam, ¶[0114]) to the second group of word lines based on the second group of word lines being assigned the second status (Applying a erase bias inhibit voltage to the second group of wordlines in the erased/unprogrammed state: Puthenthermadam, ¶[0114]).
Puthenthermadam teaches the application of different bias voltages to word lines can affect the erase speed of the programmed cells, as well as affecting erase disturbances on the unselected word lines (Puthenthermadam, ¶[0047]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the variable erase biases of Puthenthermadam with the programmed/unprogrammed memory cell determination of Lee, with a reasonable expectation of success. Both inventions are well known in the field of sub-block level erasure and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed January 7, 2026 have been fully considered but they are not persuasive.
Applicant amends the independent claims to add the limitation that the first and second debiasing voltages are to be applied during an erase operation (Amended Claims, January 7, 2026). Based on this amendment, Applicant argues the previously cited prior art no longer applies. Specifically, Applicant argues prior art Puthenthermadam discloses applying an erase bias voltage during the erase verification step, not during the erase pulse as in the present invention (Applicant’s Response, Page 7 ¶3).
Accepting, arguendo, that Applicant is correct and the erase bias voltage in Puthenthermadam only applies to the erase verification step, the submitted amendment is insufficient to differentiate the present invention. Under the broadest reasonable interpretation, an erase operation consists of a series of steps and is not restricted to the erase pulse solely. Puthenthermadam describes an example erase operation as comprising: an initial Verase, the erase pulse, an erase-verification step, a decision step, a potential step up in the erase voltage, and a conclusion through either successful erase or failure (Puthenthermadam, ¶[0099] and Figure 8B). Applying an erase bias voltage during any one of those steps would qualify as “during an erase operation.”
Therefore, Applicant’s response has been fully considered but is not persuasive. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2020/0321055 A1 to Xiang Yang: Teaching a method of program inhibit between wordlines of a memory block to prevent write disturb.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
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