DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Aitken et al. US 2009/0019329 A1 (“Aitken”).
As to claim 7, Aitken discloses an operating method of an integrated circuit including a scan chain circuit, a storage device, and control circuitry, the method comprising:
receiving, by the control circuitry, input values based on output values of a plurality of combinational logic circuits stored in the scan chain circuit in response to a first request (Figure 2 or Paragraphs 10-13 or 34-35 – e.g., running tests with connected scan chain loops 32/34/36 with test commands/signals);
sequentially providing, by the control circuitry, the input values based on the output values to the scan chain circuit (Figures 2 or Paragraphs 10-13 or 34-35 – e.g., scan chain loops 32/34/36 are sequentially connected);
receiving, by the control circuitry, input values from the storage device in response to a second request (Figure 2 or Paragraphs 10-13 or 34-35 – e.g., use of a signal decoder for test commands and/or test signals); and
sequentially providing, by the control circuitry, the input values received from the storage device to the scan chain circuit (Figure 2 or Paragraphs 10-13 or 34-35 – e.g., running multiples tests with connected scan chain loops 32/34/36 according to test commands/signals).
Allowable Subject Matter
Claims 8-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if nonelected claims 1-6 and 14-20 are cancelled.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest an operating method of an integrated circuit having the combination of elements of the claims including, among other elements, the providing of sequential input value and value storage in the order and timing of the claims, in combination with the other input and control elements of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
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/BRYCE M AISAKA/ Primary Examiner, Art Unit 2851