Prosecution Insights
Last updated: October 24, 2026
Application No. 18/528,501

INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF

Non-Final OA §102
Filed
Dec 04, 2023
Priority
Mar 24, 2023 — RE 10-2023-0039013 +1 more
Examiner
AISAKA, BRYCE M
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
659 granted / 753 resolved
+19.5% vs TC avg
Moderate +10% lift
Without
With
+10.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
16 currently pending
Career history
769
Total Applications
across all art units

Statute-Specific Performance

§101
20.2%
-19.8% vs TC avg
§103
32.7%
-7.3% vs TC avg
§102
21.1%
-18.9% vs TC avg
§112
22.6%
-17.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 753 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 7 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Aitken et al. US 2009/0019329 A1 (“Aitken”). As to claim 7, Aitken discloses an operating method of an integrated circuit including a scan chain circuit, a storage device, and control circuitry, the method comprising: receiving, by the control circuitry, input values based on output values of a plurality of combinational logic circuits stored in the scan chain circuit in response to a first request (Figure 2 or Paragraphs 10-13 or 34-35 – e.g., running tests with connected scan chain loops 32/34/36 with test commands/signals); sequentially providing, by the control circuitry, the input values based on the output values to the scan chain circuit (Figures 2 or Paragraphs 10-13 or 34-35 – e.g., scan chain loops 32/34/36 are sequentially connected); receiving, by the control circuitry, input values from the storage device in response to a second request (Figure 2 or Paragraphs 10-13 or 34-35 – e.g., use of a signal decoder for test commands and/or test signals); and sequentially providing, by the control circuitry, the input values received from the storage device to the scan chain circuit (Figure 2 or Paragraphs 10-13 or 34-35 – e.g., running multiples tests with connected scan chain loops 32/34/36 according to test commands/signals). Allowable Subject Matter Claims 8-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if nonelected claims 1-6 and 14-20 are cancelled. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach or suggest an operating method of an integrated circuit having the combination of elements of the claims including, among other elements, the providing of sequential input value and value storage in the order and timing of the claims, in combination with the other input and control elements of the claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRYCE M AISAKA/ Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Dec 04, 2023
Application Filed
Oct 16, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
98%
With Interview (+10.3%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 753 resolved cases by this examiner. Grant probability derived from career allowance rate.

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