Detailed Action
This office action is in response to the amendment filed on May 13th, 2026. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed May 13th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 11-12) that Kim and the other cited references fail to teach the limitations presented in amended Claims 1, 10, and 19.
However, as seen below, Claims 1 and 19 are rejected by the combination of Kim, Kim2, and Kim4. Claim 10 is rejected by the combination of Kim and Kim4.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Applicant’s amendments have overcome the drawing and specification objections of the previous office action.
Applicant’s amendments have overcome the 35 U.S.C. 112(a) and 112(b) rejections of the previous office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2012/0139021 A1; hereinafter Kim) in view of Kim et al. (2016/0293598 A1; hereinafter Kim2) and Kim et al. (2018/0350611 A1; hereinafter Kim4).
Regarding Claim 1, Kim (annotated figs. 15A-B) teaches a semiconductor device ([0019]), comprising:
an active pattern ([0026], 109 and 116a/116b);
an additional active layer ([0042], 126) on the active pattern (109 and 116a/116b); and
a gate structure ([0027], [0039], 110, 112, 114) running across the active pattern (109 and 116a/116b), wherein
the additional active layer (126) includes a bottom surface (bottom of 126) connected to a sidewall of the active pattern (sidewall of 109 and 116a/116b); and
an upper curved surface (upper surface of 126) above the bottom surface (bottom of 126),
a lowermost surface of the additional active layer on an uppermost surface of the gate structure, and
a lattice constant of the additional active layer is different from a lattice constant of the active pattern.
Kim doesn’t teach a lowermost surface of the additional active layer on an uppermost surface of the gate structure.
However, Kim4 (fig. 5Q) teaches a lowermost surface of the additional active layer ([0109], lowermost surface of 29) on (29 is indirectly on 16, 17, 18 through 30, see fig. 5Q) an uppermost surface of the gate structure ([0091]-[0092], uppermost surface of 16, 17, 18). Kim4 also teaches that the extension of the plug pad may be able to improve an open margin when a contact hole is formed later ([0113]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the additional active layer of Kim4 to improve an open margin.
Kim doesn’t teach that a lattice constant of the additional active layer is different from a lattice constant of the active pattern.
However, Kim2 (fig. 2) teaches a lattice constant of the additional active layer ([0054], 114b) is different ([0054], 114b may have a lower lattice constant than 112b) from a lattice constant of the active pattern ([0054], 112b). Kim2 also teaches that this difference in lattice constant provides a stress or tension required by some devices ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the lattice constant difference of Kim2 to provide a tension as required by some devices.
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Annotated Figure 15A
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Annotated Figure 15B
Regarding Claim 2, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein the gate structure (110, 112, 114) includes a gate dielectric pattern (110), and a lowermost portion of the additional active layer (bottom of 126) is in contact with the gate dielectric pattern (110).
Regarding Claim 3, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein a device isolation pattern ([0026], 104, 106, 108) defining the active pattern (109), wherein the active pattern (109 and 116a/116b) includes a first active part (part of 109 and 116a/b adjacent to 110, referred to as first active part, see annotated fig. 15A) and a second active part (part of 109 and 116a/b adjacent to 104, referred to as second active part, see annotated fig. 15B), the additional active layer (126) includes a first active layer (part of 126 above 110, referred to as first active layer, see annotated fig. 15A) and a second active layer (part of 126 above 104, referred to as second active layer, see annotated fig. 15B), the first active layer (first active layer) contacts the first active part (first active part) and at least partially overlaps the gate structure (110, 112, 114); and the second active layer (second active layer) contacts the second active part (second active part) and at least partially overlaps the device isolation pattern (104, 106, 108).
Regarding Claim 4, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 3, wherein the first active part (first active part) has a tetragonal shape (see annotated fig. 1A) when viewed in plan, and the second active part (second active part) includes a curved portion (see annotated fig. 1A) when viewed in plan.
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Annotated Figure 1A
Regarding Claim 5, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein the gate structure (110, 112, 114) includes a gate electrode (112) and a gate capping pattern (114) on the gate electrode (112), and the semiconductor device further comprises an additional capping layer ([0048], 128) in contact with the additional active layer (126) and the gate capping pattern (114).
Regarding Claim 6, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein the gate structure (110, 112, 114) includes a gate dielectric pattern (110), and a top surface of the gate dielectric pattern (upper half of the sidewall 110 below the second contact point, referred to as top surface, see annotated fig. 15A) is below an uppermost portion of the active pattern (top of 116a/116b).
Regarding Claim 7, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein the additional active layer (126) is epitaxially grown from the active pattern (109) such that there is no interface between ([0043]-[0044], 109 and 116a/116b are used as a seed layer and is extended upward by 126) the additional active layer (126) and the active pattern (109).
Regarding Claim 8, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, further comprising: a storage node contact ([0055], 138) in contact with the active pattern (138 is in electrical contact with 109 and 116a/116b through 126), wherein a lowermost portion of the additional active layer (bottom of 126) is below a lowermost portion of the storage node contact (bottom of 138).
Regarding Claim 9, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, further comprising: a device isolation pattern ([0026], 104, 106, 108) defining the active pattern (109); wherein a contact point (contact point between 126 and 109 and 116a/116b, referred to as first contact point, see annotated fig. 15B) of the sidewall of the active pattern (sidewall of 109 and 116a/116b) and the additional active layer (126) is planar with a lowermost portion of the additional active layer (bottom surface of 126 is planar and the same height).
Regarding Claim 19, Kim (annotated figs. 15A-B) teaches a semiconductor device ([0019]), comprising:
an active pattern ([0026], 109 and 116a/116b);
an additional active layer ([0042], 126) on the active pattern (109 and 116a/116b);
a gate structure ([0027], [0039], 110, 112, 114) that runs across the active pattern (109 and 116a/116b);
a device isolation pattern ([0026], 104, 106, 108) surrounding the active pattern (109 and 116a/116b); and
a storage node contact ([0055], 138) electrically connected to the additional active layer (126), wherein
the additional active layer (126) includes a bottom surface (bottom of 126) connected to a sidewall of the active pattern (sidewall of 109 and 116a/116b), a contact point (contact point between 126 and 109 and 116a/116b, referred to as first contact point, see annotated fig. 15B) of the bottom surface of the additional active layer (bottom of 126) is below a lowermost portion of the storage node contact (bottom of 138),
a lowermost surface of the additional active layer on an uppermost surface of the gate structure, and
a lattice constant of the additional active layer is different from a lattice constant of the active pattern.
Kim doesn’t teach a lowermost surface of the additional active layer on an uppermost surface of the gate structure.
However, Kim4 (fig. 5Q) teaches a lowermost surface of the additional active layer ([0109], lowermost surface of 29) on (29 is indirectly on 16, 17, 18 through 30, see fig. 5Q) an uppermost surface of the gate structure ([0091]-[0092], uppermost surface of 16, 17, 18). Kim4 also teaches that the extension of the plug pad may be able to improve an open margin when a contact hole is formed later ([0113]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the additional active layer of Kim4 to improve an open margin.
Kim doesn’t teach that a lattice constant of the additional active layer is different from a lattice constant of the active pattern.
However, Kim2 (fig. 2) teaches a lattice constant of the additional active layer ([0054], 114b) is different ([0054], 114b may have a lower lattice constant than 112b) from a lattice constant of the active pattern ([0054], 112b). Kim2 also teaches that this difference in lattice constant provides a stress or tension required by some devices ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the lattice constant difference of Kim2 to provide a tension as required by some devices.
Claims 10-12, 14-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kim4.
Regarding Claim 10, Kim (annotated figs. 15A-B) teaches a semiconductor device ([0019]), comprising:
an active pattern ([0026]-[0027], 109 and doped regions 116a/116b in 109);
an additional active layer ([0042], 126) on the active pattern (109 and 116a/116b);
a gate structure ([0027], [0039], 110, 112, 114) that runs across the active pattern (109 and 116a/116b), and
a storage node contact ([0055], 138) in contact (109 and 116a/116b electrically contacts 138 through 126) with the additional active layer (126) and the active pattern (109 and 116a/116b), wherein
the additional active layer (126) includes a bottom surface (bottom of 126) connected to a sidewall of the active pattern (sidewall of 109 and 116a/116b);
an upper curved surface (top of 126) above the bottom surface (bottom of 126);
a lateral surface (sidewall of 126) between the bottom surface (bottom of 126) and the upper curved surface (top of 126),
a lowermost surface of the additional active layer on an uppermost surface of the gate structure, and
a first contact point (contact point between 126 and 116a/116b, referred to as first contact point, see annotated fig. 15B) contacting the sidewall of the active pattern (sidewall of 109 and 116a/116b) and below a lowermost portion of the storage node contact (bottom of 138).
Kim doesn’t teach a lowermost surface of the additional active layer on an uppermost surface of the gate structure.
However, Kim4 (fig. 5Q) teaches a lowermost surface of the additional active layer ([0109], lowermost surface of 29) on (29 is indirectly on 16, 17, 18 through 30, see fig. 5Q) an uppermost surface of the gate structure ([0091]-[0092], uppermost surface of 16, 17, 18). Kim4 also teaches that the extension of the plug pad may be able to improve an open margin when a contact hole is formed later ([0113]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the additional active layer of Kim4 to improve an open margin.
Regarding Claim 11, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 10, wherein the gate structure (110, 112, 114) includes a gate dielectric pattern (110), and the gate dielectric pattern (110) and the additional active layer (126) at least partially overlap each other (see annotated fig. 15A).
Regarding Claim 12, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 11, further comprising: an additional capping layer ([0048], 128), the additional capping layer (128) at least partially covering at least one of the upper curved surface of the additional active layer, the lateral surface of the additional active layer, and a top surface of the gate dielectric pattern (top of 114).
Regarding Claim 14, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 11, further comprising: a device isolation pattern ([0026], 104, 106, 108) defining the active pattern (109 and 116a/116b), wherein the first contact point (first contact point) contacts (see annotated fig. 15B) the device isolation pattern (104, 106, 108), and the additional active layer (126) further includes a second contact point (contact point between 126 and 110, referred to as second contact point, see annotated fig. 15A) contacting the gate dielectric pattern (110).
Regarding Claim 15, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 10, further comprising: an additional capping layer ([0048], 128) at least partially covering at least one of the upper curved surface and the lateral surface of the additional active layer (top of 126), wherein the gate structure (110, 112, 114) includes a gate dielectric pattern (110); a gate electrode (112) on the gate dielectric pattern (110); and a gate capping pattern (114) on the gate electrode (112), and a bottom surface of the additional capping layer (bottom of 128) contacts a top surface of the gate dielectric pattern (top of 114).
Regarding Claim 18, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 10, further comprising: a bit-line contact ([0047], 130) connected to the active pattern (109 and 116a/116b connected through 126), wherein the first contact point (first contact point) is below (see annotated fig. 15B) a lowermost portion of the bit-line contact (bottom of 130).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to Claim 12 above, and further in view of Moon et al. (2013/0344666 A1; hereinafter Moon).
Regarding Claim 13, Kim doesn’t teach the semiconductor device of claim 12, wherein the first contact point is planar with a bottom surface of the additional capping layer.
However, Moon (fig. 25A) teaches the first contact point ([0046], contact point between 236 and 218) is planar with a bottom surface of the additional capping layer ([0056], bottom surface of 252). Moon’s method forms an additional active layer ([0046], 236) through a selective epitaxial growth process without requiring Kim’s etching process ([0039], forming of 124b) prior to forming the additional active layer (126) through a selective epitaxial growth, thus simplifying the process of Kim.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the planar structure of Moon as it simplifies the process of selective epitaxial growth of additional active layers.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Kim4 as applied to Claim 10 above, and further in view of Kim2.
Regarding Claim 16, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 10, Kim doesn’t teach the semiconductor device of claim 10, wherein a lattice constant of the additional active layer is different from a lattice constant of the active pattern.
However, Kim2 (fig. 2) teaches a lattice constant of the additional active layer ([0054], 114b) is different ([0054], 114b may have a lower lattice constant than 112b) from a lattice constant of the active pattern ([0054], 112b). Kim2 also teaches that this difference in lattice constant provides a stress or tension required by some devices ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the lattice constant difference of Kim2 to provide a tension as required by some devices.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to Claim 10 above, and further in view of Kim et al. (2016/0181198 A1; hereinafter Kim3).
Regarding Claim 17, Kim doesn’t teach the semiconductor device of claim 10, wherein the additional active layer at least partially surrounds the active pattern when viewed in plan.
However, Kim3 (fig. 53) teaches the additional active layer ([0061], 17) at least partially surrounds the active pattern ([0024], 11) when viewed in plan (17S partially surrounds 11 when viewed from above). Kim3 also teaches this increases the contact area and improves the reliability of the device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to utilize the additional active layer of Kim3 as it increases device reliability.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Kim2 as applied to Claim 19 above, and further in view of Moon.
Regarding Claim 20, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 19, further comprising: an additional capping layer ([0048], 128) at least covering at least one of an upper curved surface and a lateral surface of the additional active layer (upper surface of 126); and a gate structure ([0027], [0039], 110, 112, 114) running across the active pattern (109 and 116a/116b), wherein the gate structure (110, 112, 114) includes a gate capping pattern (114), the additional active layer (126) includes a same material ([0043], 126 may be silicon) as ([0020], substrate 100 may be silicon, later formed into 109 and 116a/116b) the active pattern (109 and 116a/116b), and the additional capping layer includes a same material as a material of the gate capping pattern.
Kim doesn’t explicitly teach that the additional capping layer includes a same material as a material of the gate capping pattern.
However, Moon (fig. 25A) teaches the additional capping layer ([0056], 252) includes a same material ([0056], 252 may be silicon oxide) as a material ([0032], 234a may be silicon oxide) of the gate capping pattern ([0032], 234a) while still obtaining the predictable results of a properly insulated semiconductor device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the materials of the gate and additional capping layers of Moon for the materials of the gate and additional capping layers of Tokita, since simple substitution of materials for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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