Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 4th, 2023, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “the active pattern includes… a second active part at least partially overlapping the device isolation pattern” in Claim 3 and the limitation “the active pattern and the additional active layer are a single unitary body with no interface therebetween” of Claim 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3 and 7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In this instance, Claim 3 recites the limitation “the active pattern including…a second active part at least partially overlapping the device isolation pattern”. While applicant’s filed specification describes that portions of the additional active layer overlap the device isolation pattern ([0071], 1121SS formed over 120), there is no discussion of portions of the active pattern also overlapping the device isolation pattern. Therefore, applicant does not have support for the limitation recited above.
In this instance, Claim 7 recites the limitation “the active pattern and the additional active layer are a single unitary body with no interface therebetween”. While applicant’s filed specification describes that portions of the additional active layer are connected with no interface therebetween ([0067], 1121 and 1122, for example), there is no discussion of the interface between the active pattern and the additional active layer. There is also no description as to what a single unitary body is and how the interface may be controlled to achieve such an effect. Therefore, applicant does not have support for the limitation recited above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "a single unitary body with no interface therebetween" in line 2. It is unclear as to what conditions are needed to be satisfied to form a single unitary body. For the purpose of examination, the limitation will be interpreted as being formed of the same material.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-12, 14-15, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (2012/0139021 A1; hereinafter Kim).
Regarding Claim 10, Kim (annotated figs. 15A-B) teaches a semiconductor device ([0019]), comprising:
an active pattern ([0026]-[0027], 109 and doped regions 116a/116b in 109);
an additional active layer ([0042], 126) on the active pattern (109 and 116a/116b); and
a storage node contact ([0055], 138) in contact (109 and 116a/116b electrically contacts 138 through 126) with the additional active layer (126) and the active pattern (109 and 116a/116b), wherein
the additional active layer (126) includes a bottom surface (bottom of 126) connected to a sidewall of the active pattern (sidewall of 109 and 116a/116b);
an upper curved surface (top of 126) above the bottom surface (bottom of 126);
a lateral surface (sidewall of 126) between the bottom surface (bottom of 126) and the upper curved surface (top of 126), and
a first contact point (contact point between 126 and 116a/116b, referred to as first contact point, see annotated fig. 15B) contacting the sidewall of the active pattern (sidewall of 109 and 116a/116b) and below a lowermost portion of the storage node contact (bottom of 138).
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Annotated Figure 15A
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Annotated Figure 15B
Regarding Claim 11, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 10, further comprising: a gate structure ([0027], [0039], 110, 112, 114) that runs across the active pattern (109 and 116a/116b), wherein the gate structure (110, 112, 114) includes a gate dielectric pattern (110), and the gate dielectric pattern (110) and the additional active layer (126) at least partially overlap each other (see annotated fig. 15A).
Regarding Claim 12, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 11, further comprising: an additional capping layer ([0048], 128), the additional capping layer (128) at least partially covering at least one of the upper curved surface of the additional active layer, the lateral surface of the additional active layer, and a top surface of the gate dielectric pattern (top of 114).
Regarding Claim 14, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 11, further comprising: a device isolation pattern ([0026], 104, 106, 108) defining the active pattern (109 and 116a/116b), wherein the first contact point (first contact point) contacts (see annotated fig. 15B) the device isolation pattern (104, 106, 108), and the additional active layer (126) further includes a second contact point (contact point between 126 and 110, referred to as second contact point, see annotated fig. 15A) contacting the gate dielectric pattern (110).
Regarding Claim 15, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 10, further comprising: a gate structure ([0027], [0039], 110, 112, 114) running across the active pattern (109 and 116a/116b); and an additional capping layer ([0048], 128) at least partially covering at least one of the upper curved surface and the lateral surface of the additional active layer (top of 126), wherein the gate structure (110, 112, 114) includes a gate dielectric pattern (110); a gate electrode (112) on the gate dielectric pattern (110); and a gate capping pattern (114) on the gate electrode (112), and a bottom surface of the additional capping layer (bottom of 128) contacts a top surface of the gate dielectric pattern (top of 114).
Regarding Claim 18, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 10, further comprising: a bit-line contact ([0047], 130) connected to the active pattern (109 and 116a/116b connected through 126), wherein the first contact point (first contact point) is below (see annotated fig. 15B) a lowermost portion of the bit-line contact (bottom of 130).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kim et al. (2016/0293598 A1; hereinafter Kim2).
Regarding Claim 1, Kim (annotated figs. 15A-B) teaches a semiconductor device ([0019]), comprising:
an active pattern ([0026], 109 and 116a/116b);
an additional active layer ([0042], 126) on the active pattern (109 and 116a/116b); and
a gate structure ([0027], [0039], 110, 112, 114) running across the active pattern (109 and 116a/116b), wherein
the additional active layer (126) includes a bottom surface (bottom of 126) connected to a sidewall of the active pattern (sidewall of 109 and 116a/116b); and
an upper curved surface (upper surface of 126) above the bottom surface (bottom of 126) [].
Kim doesn’t teach that a lattice constant of the additional active layer is different from a lattice constant of the active pattern.
However, Kim2 (fig. 2) teaches a lattice constant of the additional active layer ([0054], 114b) is different ([0054], 114b may have a lower lattice constant than 112b) from a lattice constant of the active pattern ([0054], 112b). Kim2 also teaches that this difference in lattice constant provides a stress or tension required by some devices ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the lattice constant difference of Kim2 to provide a tension as required by some devices.
Regarding Claim 2, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein the gate structure (110, 112, 114) includes a gate dielectric pattern (110), and a lowermost portion of the additional active layer (bottom of 126) is in contact with the gate dielectric pattern (110).
Regarding Claim 3, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, further comprising: a device isolation pattern ([0026], 104, 106, 108) defining the active pattern (109), wherein the active pattern (109 and 116a/116b) includes a first active part (part of 109 under 110, referred to as first active part, see annotated fig. 15A) at least partially overlapping the gate structure (110, 112, 114); and a second active part (part of 126 over 104, referred to as a second active part, see annotated fig. 15B) at least partially overlapping the device isolation pattern (104, 106, 108).
Regarding Claim 4, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 3, wherein the first active part (first active part) has a tetragonal shape (see annotated fig. 1A) when viewed in plan, and the second active part (second active part) includes a curved portion (see annotated fig. 1A) when viewed in plan.
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Annotated Figure 1A
Regarding Claim 5, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein the gate structure (110, 112, 114) includes a gate electrode (112) and a gate capping pattern (114) on the gate electrode (112), and the semiconductor device further comprises an additional capping layer ([0048], 128) in contact with the additional active layer (126) and the gate capping pattern (114).
Regarding Claim 6, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein the gate structure (110, 112, 114) includes a gate dielectric pattern (110), and a top surface of the gate dielectric pattern (upper half of the sidewall 110 below the second contact point, referred to as top surface, see annotated fig. 15A) is below an uppermost portion of the active pattern (top of 116a/116b).
Regarding Claim 7, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, wherein the active pattern (109 and 116a/116b) and the additional active layer (126) are a single unitary body with no interface therebetween ([0043]-[0044], 109 and 116a/116b are used as a seed layer and is extended upward by 126).
Regarding Claim 8, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, further comprising: a storage node contact ([0055], 138) in contact with the active pattern (138 is in electrical contact with 109 and 116a/116b through 126), wherein a lowermost portion of the additional active layer (bottom of 126) is below a lowermost portion of the storage node contact (bottom of 138).
Regarding Claim 9, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 1, further comprising: a device isolation pattern ([0026], 104, 106, 108) defining the active pattern (109); wherein a contact point (contact point between 126 and 109 and 116a/116b, referred to as first contact point, see annotated fig. 15B) of the sidewall of the active pattern (sidewall of 109 and 116a/116b) and the additional active layer (126) is planar with a lowermost portion of the additional active layer (bottom surface of 126 is planar and the same height).
Regarding Claim 16, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 10, Kim doesn’t teach the semiconductor device of claim 10, wherein a lattice constant of the additional active layer is different from a lattice constant of the active pattern.
However, Kim2 (fig. 2) teaches a lattice constant of the additional active layer ([0054], 114b) is different ([0054], 114b may have a lower lattice constant than 112b) from a lattice constant of the active pattern ([0054], 112b). Kim2 also teaches that this difference in lattice constant provides a stress or tension required by some devices ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the lattice constant difference of Kim2 to provide a tension as required by some devices.
Regarding Claim 19, Kim (annotated figs. 15A-B) teaches a semiconductor device ([0019]), comprising:
an active pattern ([0026], 109 and 116a/116b);
an additional active layer ([0042], 126) on the active pattern (109 and 116a/116b);
a device isolation pattern ([0026], 104, 106, 108) surrounding the active pattern (109 and 116a/116b); and
a storage node contact ([0055], 138) electrically connected to the additional active layer (126), wherein
the additional active layer (126) includes a bottom surface (bottom of 126) connected to a sidewall of the active pattern (sidewall of 109 and 116a/116b), a contact point (contact point between 126 and 109 and 116a/116b, referred to as first contact point, see annotated fig. 15B) of the bottom surface of the additional active layer (bottom of 126) is below a lowermost portion of the storage node contact (bottom of 138) [].
Kim doesn’t teach that a lattice constant of the additional active layer is different from a lattice constant of the active pattern.
However, Kim2 (fig. 2) teaches a lattice constant of the additional active layer ([0054], 114b) is different ([0054], 114b may have a lower lattice constant than 112b) from a lattice constant of the active pattern ([0054], 112b). Kim2 also teaches that this difference in lattice constant provides a stress or tension required by some devices ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the lattice constant difference of Kim2 to provide a tension as required by some devices.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to Claim 12 above, and further in view of Moon et al. (2013/0344666 A1; hereinafter Moon).
Regarding Claim 13, Kim doesn’t teach the semiconductor device of claim 12, wherein the first contact point is planar with a bottom surface of the additional capping layer.
However, Moon (fig. 25A) teaches the first contact point ([0046], contact point between 236 and 218) is planar with a bottom surface of the additional capping layer ([0056], bottom surface of 252). Moon’s method forms an additional active layer ([0046], 236) through a selective epitaxial growth process without requiring Kim’s etching process ([0039], forming of 124b) prior to forming the additional active layer (126) through a selective epitaxial growth, thus simplifying the process of Kim.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to include the planar structure of Moon as it simplifies the process of selective epitaxial growth of additional active layers.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to Claim 10 above, and further in view of Kim et al. (2016/0181198 A1; hereinafter Kim3).
Regarding Claim 17, Kim doesn’t teach the semiconductor device of claim 10, wherein the additional active layer at least partially surrounds the active pattern when viewed in plan.
However, Kim3 (fig. 53) teaches the additional active layer ([0061], 17) at least partially surrounds the active pattern ([0024], 11) when viewed in plan (17S partially surrounds 11 when viewed from above). Kim3 also teaches this increases the contact area and improves the reliability of the device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Kim to utilize the additional active layer of Kim3 as it increases device reliability.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Kim2 as applied to Claim 19 above, and further in view of Moon.
Regarding Claim 20, Kim (annotated figs. 15A-B) teaches the semiconductor device of claim 19, further comprising: an additional capping layer ([0048], 128) at least covering at least one of an upper curved surface and a lateral surface of the additional active layer (upper surface of 126); and a gate structure ([0027], [0039], 110, 112, 114) running across the active pattern (109 and 116a/116b), wherein the gate structure (110, 112, 114) includes a gate capping pattern (114), the additional active layer (126) includes a material ([0043], 126 may be silicon) that is the same as a material ([0020], substrate 100 may be silicon, later formed into 109 and 116a/116b) of the active pattern (109 and 116a/116b) [].
Kim doesn’t explicitly teach that the additional capping layer includes a material that is the same as a material of the gate capping pattern.
However, Moon (fig. 25A) teaches the additional capping layer ([0056], 252) includes a material ([0056], 252 may be silicon oxide) that is the same as a material ([0032], 234a may be silicon oxide) of the gate capping pattern ([0032], 234a) while still obtaining the predictable results of a properly insulated semiconductor device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the materials of the gate and additional capping layers of Moon for the materials of the gate and additional capping layers of Tokita, since simple substitution of materials for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 11, 2026