DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 1, 2, 4, 8, 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo et al. (10657892) in view of Toyota et al. (7791695).
With regard to claim 1, Woo et al. disclose a display apparatus (for example, see figs. 2, 7, 9) comprising:
a substrate (10) including a plurality of sub-pixels (PX, figs. 2, 7, 9);
a thin film transistor (for example, see transistor T1, figs. 2, 9) and a light emitting element (OLED, fig. 2) disposed in each of the sub-pixels (PX) over the substrate (10); and
a plurality of capacitors (Cst, Cse) disposed in parallel on a same plane (a top surface plane of the layer 11, fig. 9 functions as a same plane) in the sub-pixel (PX as shown in fig. 9 below);
wherein each of the plurality of capacitors (Cst, Cse) includes a first capacitor electrode (Cse11, Cse21, or Cst11. Cst21), a second capacitor electrode (Cse12, Cse22, or Cst12. Cst22), and an interlayer insulating layer (13) between the first capacitor electrode (Cse11, Cse21, or Cst11. Cst21) and the second capacitor electrode (Cse12, Cse22, or Cst12. Cst22).
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Woo et al. do not clearly disclose the first capacitor electrodes of the plurality of capacitors are electrically connected to each other, and wherein the second capacitor electrodes of the plurality of capacitors are electrically connected to each other.
However, Toyota et al. disclose the first capacitor electrodes (PX(t), PX(r)) of the plurality of capacitors (C1, C2) are electrically connected to each other (fig. 2), and wherein the second capacitor electrodes (CT(t), CT(r)) of the plurality of capacitors (C1, C2) are electrically connected to each other (fig. 2). (for example, see figs. 1, 2).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Woo et al.’s device to have the first capacitor electrodes of the plurality of capacitors are electrically connected to each other, and wherein the second capacitor electrodes of the plurality of capacitors are electrically connected to each other as taught by Toyota et al. in order to enhance a high capacitance of the capacitors of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 2, Woo et al. disclose the thin film transistor includes; a semiconductor layer (a semiconductor layer C11 including a channel region C11) on the substrate (10); a gate insulating layer (12) on the semiconductor layer (the semiconductor layer C11 including the channel region C11); a gate electrode (G11) on the gate insulating layer (12); and a source electrode (a source region S11 functioning as a source electrode) and a drain electrode (a drain region D11 functioning as a drain electrode) on (on a bottom surface of the interlayer insulating layer (13) or a source electrode (S1, fig. 7) and a drain electrode (D1) on (on a top or a bottom surface of the interlayer insulating layer (13).
With regard to claim 4, Woo et al. disclose each of the plurality of capacitors (Cst, Cse) includes: the first capacitor electrode (Cst11, Cst21) is disclosed on the gate insulating layer (12); the first capacitor electrode (Cst11, Cst21) is overlapped with the second capacitor electrode (Cst12, Cse22) with the interlayer insulating layer (13) therebetween.
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With regard to claim 8, Woo et al. disclose the plurality of capacitors (Cst, Cse) are disposed in one side (an upper side) of a region in which the thin film transistor (T1) is formed in the sub-pixel (PX).
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With regard to claim 10, Woo et al. disclose the plurality of capacitors (Cst, Cse) are disposed in both sides (upper and lateral sides) of the portion in which the thin film transistor (T1) is formed in the sub-pixel (PX).
With regard to claim 11, Woo et al. disclose light emitting element (OLED, fig. 2) is an organic light emitting device.
3. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Woo et al. (10657892) in view of Toyota et al. (7791695) and further in view of Lee (11335755).
With regard to claim 5, Woo et al. disclose the first capacitor electrode (Cst11, Cst21) is formed of a same material as the gate electrode (G11, G12), but Woo et al. do not clearly disclose the second capacitor electrode is formed of a same material as the drain electrode.
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However, Lee discloses the second capacitor electrode (referred to as “CAP2” by examiner’s annotation shown in fig. 3 below) of the capacitor (CAP) is formed of a same material as the drain electrode (160d). (for example, see column 11, lines 27 – 30, fig. 3).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Woo et al. and Toyota et al.’s device to have the second capacitor electrode is formed of a same material as the drain electrode as taught by Lee in order to have the same process reducing a cost of manufacturing and enhance a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
4. Claims 6, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Woo et al. (10657892) and Toyota et al. (7791695) and Lee (11335755) and further in view of Sun (2005/0275352).
With regard to claims 6, 7, Woo et al., Toyota et al., and Lee do not clearly disclose the first capacitor electrode of the plurality of capacitors is connected to a first signal line connected to the gate electrode and the second capacitor electrode of the plurality of capacitors is connected to a second signal line connected to the source electrode wherein at least one of a connection of the first capacitor electrode and the first signal line and a connection of the second capacitor electrode and the second signal line is disconnected in a defective capacitor of the plurality of capacitors.
However, Sun discloses the first capacitor electrode (referred to as “18A1” by examiner’s annotation shown in fig. 7B below) of the plurality of capacitors (18, 16) is connected to a first signal line (referred to as “SL1” by examiner’s annotation shown in fig. 7B below) connected to the gate electrode (referred to as “S20A1” by examiner’s annotation shown in fig. 7B below) and the second capacitor electrode (referred to as “18A2” by examiner’s annotation shown in fig. 7B below) of the plurality of capacitors (18, 16) is connected to a second signal line (referred to as “SL2” by examiner’s annotation shown in fig. 7B below) connected to the source electrode (referred to as “S1” by examiner’s annotation shown in fig. 7B below; wherein a current flow from a high voltage Vdd to a low voltage Vss. Therefore, the wire portion S1 inherently functioning as a source electrode; for example, see paragraph [0008]) wherein a connection (referred to as “16A1” by examiner’s annotation shown in fig. 7B below) of the first capacitor electrode (18A1) and the first signal line (SL1) is disconnected in a defective capacitor (for example, see paragraphs [0035], [0036]) of the plurality of capacitors (18, 16).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Woo et al., Toyota et al., and Lee’s device to have the first capacitor electrode of the plurality of capacitors is connected to a first signal line connected to the gate electrode and the second capacitor electrode of the plurality of capacitors is connected to a second signal line connected to the source electrode wherein at least one of a connection of the first capacitor electrode and the first signal line and a connection of the second capacitor electrode and the second signal line is disconnected in a defective capacitor of the plurality of capacitors as taught by Sun in order to enhance a stability operation of the semiconductor device when a capacitor for a pixel current is open-circuited or short-circuited, as is known to one of ordinary skill in the art.
5. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Woo et al. (10657892) in view of Toyota et al. (7791695) and further in view of Han et al. (9935163).
With regard to claim 9, Woo et al. disclose two capacitors (Cst, Cse) are formed by overlapping one first capacitor electrode (Cst11) and two second capacitor electrodes (Cse11, Cse12).
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Woo et al. do not clearly disclose a finger portion is formed in each of the two second capacitor electrodes to interlock with each other.
However, Han et al. disclose a finger portion (end portion of the capacitor electrode functions as a finger portion) is formed in each of the two second capacitor electrodes (221, 222, 223, 235B) to interlock with each other. (for example, see fig. 2).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Woo et al. and Toyota et al.’s device to have the second capacitor electrode is formed of a same material as the drain electrode as taught by Han et al. in order to enhance a high capacitance of the capacitor of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
6. Claims 12 – 15, 17 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as at least one of the capacitors is electrically disconnected from a first signal line connected to a gate electrode of the thin film transistor or is electrically disconnected from a second signal line connected to a source electrode of the thin film transistor, wherein remaining one of the capacitors are electrically connected to both the first signal line connected to the gate electrode of the thin film transistor and to the second signal line connected to the source electrode of the thin film transistor, and wherein two capacitors of the plurality of capacitors are formed by overlapping one first capacitor electrode and two second capacitor electrodes, and a finger portion is formed in each of the two second capacitor electrodes to interlock with each other in a plan view of the display apparatus as recited in claim 12.
Response to Amendment
7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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