DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 1, the limitation “a passive device over vertically stacked epitaxial layers … wherein a backside of the passive device … [is] directly in contact with a backside metal via a bottom interlayer dielectric” renders the claim indefinite. A claim may be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. See MPEP 2173.03.
In Fig. 1, the passive device 110B is formed in and not “over” the vertically stacked epitaxial layers. If the lower vertically stacked epitaxial layers are interpreted as separate from the passive device, so the passive device is over the lower vertically stacked epitaxial layers, then the passive device is not/can not be directly in contact with the bottom interlayer dielectric. Dependent claim 18 specifies that the passive device is isolated from the vertically stacked epitaxial layers via a silicon layer, visible as Si layer 142 in Fig. 1. In light of the entire disclosure, claim 1 will be interpreted as requiring that “a backside of the vertically stacked epitaxial layers … are directly in contact with a backside metal via a bottom interlayer dielectric”. Claims 2-9 depend from and further limit independent claim 1 and are therefore correspondingly indefinite.
Regarding claim 3, the limitation “each electrode” renders the claim indefinite, as no electrodes have been specified. For purposes of examination, the limitation will be interpreted as “wherein the P/N junction diode comprises electrodes and each electrode…”. Further, the limitation “a gate electrode of the vertically stacked epitaxial layers” renders the claim indefinite, as how the gate electrode can be “of” the vertically stacked epitaxial layers is unclear. For purposes of examination this will be interpreted as the gate electrode on the vertically stacked epitaxial layers. Claim 12 comprises the same limitations and will be interpreted correspondingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-11, and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PGPub 2018/0102359) in view of Hong (U.S. PGPub 2023/0361112) and Yang (U.S. PGPub 2024/0282670).
Regarding claim 1, Cheng teaches a semiconductor device (Fig. 9), comprising a passive device (140, [0034], P/N junction diode) and a FET adjacent to the passive device (130, [0034]).
Cheng does not explicitly teach wherein the passive device is over vertically stacked epitaxial layers of a first material and second material and wherein a backside of the vertically stacked epitaxial layers and a backside of the FET are directly in contact with a backside metal via a bottom interlayer dielectric.
Cheng teaches wherein the passive device is formed in vertically stacked epitaxial layers of a first material and second material ([0026], [0030], 108/354, Si; [0032], 402, SiGe).
Hong teaches a passive device formed in and over vertically stacked epitaxial layers (Fig. 2, [0018], first stack S1/second stack S2, [0018]; [0004] first stack includes P-N junction diode and dummy stack; [0033] dummy stack S2, [0018], stacked epitaxial layers 14_2) and a FET adjacent to the passive device ([0037], TS1).
Hong further teaches wherein the backside of the vertically stacked epitaxial layers and a backside of the FET are connected to a backside metal (Fig. 6, [0065]) and wherein the FET comprises stacked transistors ([0037]).
Yang teaches wherein a FET comprising stacked transistors is directly in contact with a backside metal via a bottom interlayer dielectric (Fig. 1B, [0032] transistors 100U/L; [0039]-[0040] bottom ILD 106; [0086] backside contact connects to backside metal line below).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hong and Yang with Cheng such that the passive device is over vertically stacked epitaxial layers of a first material and second material and wherein a backside of the vertically stacked epitaxial layers and a backside of the FET are directly in contact with a backside metal via a bottom interlayer dielectric for the purpose of providing the P/N junction diode of Cheng in a device with stacked transistors (Hong, [0037]) and providing a backside power rail for stacked transistors (Yang, [0006]).
Regarding claim 2, the combination of Cheng, Hong, and Yang teaches wherein the passive device is a P/N junction diode (Cheng, [0034]; Hong, [0004]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 1.
Regarding claim 4, the combination of Cheng, Hong, and Yang teaches wherein the passive device is a junction diode (Cheng, [0034]; Hong, [0004]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Cheng, Hong, and Yang teaches wherein the first material includes Si, and the second material includes SiGe (Cheng, [0026], [0030], 108/354, Si; [0032], 402, SiGe). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Cheng, Hong, and Yang teaches wherein the FET is a vertically stacked FET and the vertically stacked FET includes a top nanosheet FET stacked over a bottom nanosheet FET (Hong, [0037], Yang, [0032]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 1.
Regarding claim 7, the combination of Cheng, Hong, and Yang teaches wherein S/D regions of the top nanosheet FET are connected to a frontside of the semiconductor device via top S/D contacts and a gate region of the top nanosheet FET is connected to the frontside of the semiconductor device via a top gate contact (Yang, Figs. 1A-1C, top S/D contacts 127, top gate contact 128, [0036]-[0037]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Cheng, Hong, and Yang teaches wherein an S/D region of the bottom nanosheet FET is connected to a backside of the semiconductor device via backside contact (Yang, Fig. 1B, 107, [0039]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 1.
Regarding claim 9, the combination of Cheng, Hong, and Yang teaches wherein the passive device is separated from the vertically stacked epitaxial layers via a silicon layer (Cheng, Fig. ; Hong, Fig. 2; extending the stack of Cheng to include the dummy stack of Hong will comprise a silicon layer at the bottom of the stack of Cheng. The vertically stacked epitaxial layers may be defined as the remaining stack). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 1.
Regarding claim 10, Cheng teaches a method for forming a semiconductor device (Fig. 9), comprising forming a passive device over a substrate (140, [0034], P/N junction diode) and forming a FET adjacent to the passive device (130, [0034]).
Cheng does not explicitly teach wherein the passive device is formed over vertically stacked epitaxial layers of a first material and second material, removing the substrate, and forming a bottom interlayer dielectric (BILD) over a backside of the passive device and a backside of the FET.
Cheng teaches wherein the passive device is formed in vertically stacked epitaxial layers of a first material and second material ([0026], [0030], 108/354, Si; [0032], 402, SiGe).
Hong teaches a passive device formed in and over vertically stacked epitaxial layers (Fig. 2, [0018], first stack S1/second stack S2, [0018]; [0004] first stack includes P-N junction diode and dummy stack; [0033] dummy stack S2, [0018], stacked epitaxial layers 14_2) and a FET adjacent to the passive device ([0037], TS1).
Hong further teaches wherein the backside of the vertically stacked epitaxial layers and a backside of the FET are connected to a backside metal (Fig. 6, [0065]) and wherein the FET comprises stacked transistors ([0037]).
Yang teaches forming a FET comprising stacked transistors over a substrate (Figs. 11A-11B, 105, [0052], [0077]), removing the substrate, and forming a bottom interlayer dielectric (BILD) over a backside of the FET (Figs. 12A-12B, 106, [0080]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hong and Yang with Cheng such that the passive device is formed over vertically stacked epitaxial layers of a first material and second material, removing the substrate, and forming a bottom interlayer dielectric (BILD) over a backside of the passive device and a backside of the FET for the purpose of providing the P/N junction diode of Cheng in a device with stacked transistors (Hong, [0037]) and providing a backside power rail for stacked transistors (Yang, [0006]).
Regarding claim 11, the combination of Cheng, Hong, and Yang teaches wherein the passive device is a P/N junction diode (Cheng, [0034]; Hong, [0004]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 10.
Regarding claim 13, the combination of Cheng, Hong, and Yang teaches wherein the passive device is a junction diode (Cheng, [0034]; Hong, [0004]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 10.
Regarding claim 14, the combination of Cheng, Hong, and Yang teaches wherein the first material includes Si, and the second material includes SiGe (Cheng, [0026], [0030], 108/354, Si; [0032], 402, SiGe). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 10.
Regarding claim 15, the combination of Cheng, Hong, and Yang teaches wherein forming the FET comprises stacking a top nanosheet FET over a bottom nanosheet FET (Hong, [0037], Yang, [0032]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 10.
Regarding claim 16, the combination of Cheng, Hong, and Yang teaches connecting S/D regions of the top nanosheet FET to a frontside of the semiconductor device via top S/D contacts; and
connecting a gate region of the top nanosheet FET to the frontside of the semiconductor device via a top gate contact (Yang, Figs. 1A-1C, top S/D contacts 127, top gate contact 128, [0036]-[0037]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 10.
Regarding claim 17, the combination of Cheng, Hong, and Yang teaches connecting an S/D region of the bottom nanosheet FET to a backside of the semiconductor device via backside contact (Yang, Fig. 1B, 107, [0039]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 10.
Regarding claim 18, the combination of Cheng, Hong, and Yang teaches isolating the passive device from the vertically stacked epitaxial layers via a silicon layer (Cheng, Fig. 9; Hong, Fig. 2; extending the stack of Cheng to include the dummy stack of Hong will comprise a silicon layer at the bottom of the stack of Cheng. The vertically stacked epitaxial layers may be defined as the remaining stack). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 10.
Regarding claim 19, the combination of Cheng, Hong, and Yang teaches forming a bottom metal over a bottom surface of the BILD (Yang, [0086], backside metal line, [0006]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hong, and Yang for the reasons set forth in the rejection of claim 10.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PGPub 2018/0102359) in view of Hong (U.S. PGPub 2023/0361112), Yang (U.S. PGPub 2024/0282670), and Thomson (U.S. PGPub 2023/0087444).
Regarding claim 3, the combination of Cheng, Hong, and Yang teaches wherein the P/N junction diode comprises electrodes (Cheng, Fig. 9, [0034]) but does not explicitly teach wherein each electrode of the P/N junction diode is separated by a gate electrode of the vertically stacked epitaxial layers.
Thomson teaches wherein a P/N junction diode formed over vertically stacked epitaxial layers comprises electrodes separated by a gate electrode over the vertically stacked epitaxial layers (Fig. 1a, [0036]-[0037], epitaxial layers 101a/b, gate 108).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Thomson with Cheng, Hong, and Yang such that each electrode of the P/N junction diode is separated by a gate electrode of the vertically stacked epitaxial layers for the purpose of using the same processes for the diode and transistors (Thomson, [0041]).
Regarding claim 12, the combination of Cheng, Hong, and Yang teaches wherein the P/N junction diode comprises electrodes (Cheng, Fig. 9, [0034]) but does not explicitly teach separating each electrode of the P/N junction diode by a gate electrode of the vertically stacked epitaxial layers.
Thomson teaches wherein a P/N junction diode formed over vertically stacked epitaxial layers comprises electrodes separated by a gate electrode over the vertically stacked epitaxial layers (Fig. 1a, [0036]-[0037], epitaxial layers 101a/b, gate 108).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Thomson with Cheng, Hong, and Yang such that the method comprises separating each electrode of the P/N junction diode by a gate electrode of the vertically stacked epitaxial layers for the purpose of using the same processes for the diode and transistors (Thomson, [0041]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PGPub 2018/0102359) in view of Hong (U.S. PGPub 2023/0361112).
Regarding claim 20, Cheng teaches a semiconductor device (Fig. 9), comprising a passive device over a substrate (140, [0034], P/N junction diode) and a FET adjacent to the passive device (130, [0034]).
Cheng does not explicitly teach wherein the substrate includes vertically stacked epitaxial layers of a first material and a second material and the passive device is separated from the vertically stacked epitaxial layers via a silicon layer.
Cheng teaches wherein the passive device is formed in vertically stacked epitaxial layers of a first material and second material ([0026], [0030], 108/354, Si; [0032], 402, SiGe).
Hong teaches a passive device formed in and over vertically stacked epitaxial layers (Fig. 2, [0018], first stack S1/second stack S2, [0018]; [0004] first stack includes P-N junction diode and dummy stack; [0033] dummy stack S2, [0018], stacked epitaxial layers 14_2) and a FET adjacent to the passive device ([0037], TS1).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hong with Cheng such that the substrate includes vertically stacked epitaxial layers of a first material and a second material and the passive device is separated from the vertically stacked epitaxial layers via a silicon layer for the purpose of providing the P/N junction diode of Cheng in a device with stacked transistors (Hong, [0037]; extending the stack of Cheng to include the dummy stack of Hong will comprise a silicon layer at the bottom of the stack of Cheng. The vertically stacked epitaxial layers may be defined as the remaining stack).
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
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