DETAILED ACTION
This action is responsive to the Amendments filed January 15, 2026. Prior to entry of the amendments, claims 1-20 were pending, with claims 10-15 being withdrawn from consideration as being directed to non-elected inventions. Claim 2, and 16-20 have been cancelled. Claim 1 has been amended. Claims 21-26 are new. Thus, upon entry, claims 1, 3-9, 10-15 and 21-26 are now pending. Claims 10-15 are withdrawn from consideration. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/15/26 has been entered.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 21, 2026. This IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: 3D Monolithic Non-Volatile Memory Device.
Claim Objections
Claims 3-4, and 6 are objected to because of the following informalities: The claims recite claim 2 as the base claim for these dependent claims but claim 2 has been cancelled herein. Because previously presented claim 2 was incorporated in its entirety into the amendment of independent claim 1, this deficiency appears to be an inadvertent typographical error and for purposes of examination, the base claim will be taken to mean claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 22, the phrase “gradually arranged” is a relative phrase which renders the claim indefinite. The phrase “gradually arranged” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation of how the steps are arranged in the column direction is unclear.
For purposes of compact prosecution (see MPEP 2173.06) the phrase "gradually arranged" will be taken to mean "tiered".
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-9 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicone Channel; “Huang” – of Record) in view of Titus et al. (US 20220208785; "Titus").
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Regarding independent claim 1, Huang discloses a memory block, comprising:
A substrate (Fig. 2b. See also col. 1, p. 1875; "The 3D NOR flash was fabricated on a 200 mm Si wafer").
a memory array, arranged on the substrate and comprising a plurality of memory cells distributed in a three-dimensional array, wherein the memory array comprises a plurality of memory subarray layers sequentially stacked along a height direction, and each memory subarray layer comprises a drain-region semiconductor layer, a channel semiconductor layer, and a source-region semiconductor layer stacked along the height direction (Fig. 2a & 2f. See also Abst; "A novel 3D NOR memory array";
each drain-region semiconductor layer comprises a plurality of drain-region semiconductor strips distributed along a row direction, each channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along the row direction, and each source-region semiconductor layer comprises a plurality of source-region semiconductor strips distributed along the row direction (Fig 2a - 2f);
each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip extend along a column direction respectively (Fig. 2. It is noted that this limitation appears to merely define the drain, channel, source layer group as existing in the X-Y plane as illustrated in Huang);
drain-region semiconductor strips, channel semiconductor strips, and source-region semiconductor strips in the same column of the memory subarray layers is defined as a semiconductor-strip-structure column (Fig. 2. It is noted that the term "semiconductor strip structure column" is defined in the specification of the instant application as "a stacked structure 1b" and illustrated in Fig. 3 (Spec. para. 78), which is analogous to the layered stack up in Huang's Fig. 2(a). It is further noted that the structured topology of Huang’s basic 4 transistor building block is identical to the instant application (see Examiner’s Markup above)); and
each well-connection structure corresponds to a corresponding semiconductor-strip-structure column, for electrically connecting the channel semiconductor strips in the corresponding semiconductor-strip-structure column together by using the stepped structure in the corresponding semiconductor-strip-structure column, and then leads out the channel semiconductor strips in the corresponding semiconductor-strip-structure column (Fig. 1(a). It is noted that the well-connection structure as well as other features are indicated in the specification of the instant application to be directed to Fig. 45 (Spec. para. 310) and specifically, as element 111 (filling layer) and 112 (well-connection columns). These are analogous to the column structures in Huang's Fig. 1(a) which are connected to BL1 and BL0 for example. Additional, with respect specifically to the claimed well-lead-out pad of claim 16, the elements BL0 or BL1 of Huang are analogous to the element top 112 as defined in the instant application Spec. para. 319).
wherein at least part of each channel semiconductor strip in each semiconductor-strip-structure column is exposed through the stepped structure thereof (Fig. 2(f), where it illustrates the channel connected to body terminal B1);
While Huang discloses the structure of a stepped contact structure for leading out the connections for the semiconductor layers, an explicit connecting layer covering the tiered structure is not taught.
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However, Titus teaches a well-lead-out region, comprising a plurality of well-connection structures, wherein each semiconductor-strip-structure column extends to the well-lead-out region (Fig. 3. contact region 300. See also para 52; "The terrace region is formed in the contact region 300, which is located between the memory array region 100 and the peripheral device region 200". It is noted that this element appears to be directed to Fig. 47 (well-lead-out region));
in the well-lead-out region, each semiconductor-strip-structure column comprises a stepped structure with a plurality of steps (Fig.3);
and each well-connection structure comprises a connecting layer, the connecting layer covers the stepped structure of the corresponding semiconductor-strip-structure column and connects the channel semiconductor strips in the corresponding semiconductor-strip-structure column together (Fig. 3: element 65. See also para 55; "A retro-stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein." This feature appears to be directed to Fig. 47 of the instant application and specifically element 121 which is identified as the connecting layer and is analogous to Titus's dielectric material portion 65).
Huang and Titus are from the same field of endeavor as applicants’ invention being directed to 3D memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang’s semiconductor stacks with Titus’s tiered stepped contact region with connecting layer. Doing so would improve semiconductor device density.
Regarding claim 3, Huang and Titus combined disclose the limitations of claim 1.
As applied, Huang further discloses each step comprises a first surface and a second surface, the first surface is parallel to the substrate, and the second surface is perpendicular to the substrate (Fig. 2(c), where it illustrates the bottom of the body contact hole that is parallel to the substrate);
the first surface of each step is configured to expose at least part of a corresponding channel semiconductor strip in the corresponding semiconductor-strip-structure column and the second surface of each step is covered by an insulating dielectric, to avoid exposing the drain-region semiconductor strips and the source-region semiconductor strips in the corresponding semiconductor-strip-structure column (Fig. 2(c), where it illustrates the side of the body contact hole which is perpendicular to the substrate and is covered by an oxide spacer (insulating));
the connecting layer is configured to cover the stepped structure, contact the part of the corresponding channel semiconductor strip exposed through the first surface of each step, and be insulated from the drain-region semiconductor strips and the source-region semiconductor strips in the corresponding semiconductor-strip-structure column through the insulating dielectric (Fig. 2(d) and 2(e), where it illustrates the tungsten plug connecting layer inside the oxide insulating layer and protruding through the top (insulating dielectric) oxide layer).
Regarding claim 4, Huang and Titus disclose the limitations of claim 1.
As applied, Huang further discloses wherein the connecting layer.
Huang does not expressly indicate the material of the connecting layer as polycrystalline silicon or the use of other materials.
However, Huang’s Fig. 2(d) illustrates the tungsten plugs forming the connecting layer.
In the field of 3D memory device manufacturing, it is well understood that there are many possible electrically conducting materials which may be used to form connecting layers of which polycrystalline silicon and tungsten are both common material variants exhibiting common similar deposition and conduction suitability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a connecting layer using tungsten instead of polysilicon, because tungsten and polysilicon are obvious variants due to their analogous material characteristics with respect to memory device manufacturing.
Regarding claim 5, Huang and Titus combined disclose the limitations of claim 4.
Huang is silent with respect to the specific doping of the drain, source and channel strips.
However, Titus teaches a doping type of the connecting layer is the same as that of the channel semiconductor strip and is opposite to that of the drain-region semiconductor strip and the source-region semiconductor strip (para 119; "a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores 62. The deposited semiconductor material can have a doping of a second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa". It is well understood in the art that the doping of the source and drain of the transistors is opposite polarity of the doping of the channel).
Regarding claim 6, Huang and Titus disclose the limitations of claim 1.
As applied, Huang further discloses each well-connection structure further comprises a connection-improvement layer arranged on the connecting layer, and the connection-improvement layer is a metal-silicide layer (Fig. 2(c), Silicide connection improvement layer at the bottom of the connection layer hole).
Regarding claim 7, Huang and Titus disclose the limitations of claim 1.
As applied, Huang further discloses each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip are single-crystal semiconductor strips respectively (Abstr. "To obtain single-crystal silicon channel for 3D NOR, 1) vertical flash devices were presented, 2) a stack with multiple doped epitaxial Si layers was used for making the vertical devices." It is noted that the single-crystal silicon layers comprise drain, channel and source strips as illustrated in fig. 2 and analogous to the layers in the instant application).
Regarding claim 8, Huang and Titus disclose the limitations of claim 1.
As applied, Huang further discloses along the height direction, two adjacent memory subarray layers comprise one drain-region semiconductor layer, one channel semiconductor layer, one source-region semiconductor layer, another channel semiconductor layer, and another drain-region semiconductor layer sequentially stacked to share the same source-region semiconductor layer (Fig. 2(a); and
an interlayer isolation layer is arranged between every two adjacent memory subarray layers and another two adjacent memory subarray layers to isolate every two adjacent memory subarray layers from another two adjacent memory subarray layers (Fig. 2(a) where it illustrates the oxide (isolation) layer at the top of the two layer memory stack. Also see col. 1; "It should be mentioned that although only two-layers of vertical flash devices were experimentally demonstrated in this work, our 3D NOR flash has the potential to be stacked with dozens or even hundreds of layers. And the continuous stacking will not degrade the read current, so fast-read still can be realized." It is noted that with the additional stacking indicated, the Huang's oxide isolation layer would necessarily be between every two adjacent memory sub-array layers and analogous to the isolation layer 14a of Fig. 4 in the instant application).
Regarding claim 9, Huang and Titus disclose the limitations of claim 1.
As applied, Huang further discloses an interlayer-dielectric layer, covering the memory array and the well-lead-out region, wherein, in the well-lead-out region, the interlayer-dielectric layer has at least one lead-out hole corresponding to each well-connection structure, a connecting column is arranged in the lead-out hole, one end of the connecting column is connected to a corresponding well-connection structure, and the other end of the connecting column is exposed outside the interlayer-dielectric layer to serve as a lead-out pad (Fig. 1).
Regarding claim 21, Huang and Titus disclose the limitations of claim 1.
As applied, Titus further discloses each drain-region semiconductor strip and each source-region semiconductor strip are semiconductor strips with a first doping type, and each channel semiconductor strip is a semiconductor strip with a second doping type (para 119; "a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores 62. The deposited semiconductor material can have a doping of a second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa". It is well understood in the art that the doping of the source and drain of the transistors is opposite polarity of the doping of the channel).
Regarding claim 22, Huang and Titus disclose the limitations of claim 1.
As applied, Titus further discloses wherein the steps comprised in the stepped structure are gradually arranged along the column direction (Fig. 3).
Regarding claim 23, Huang and Titus disclose the limitations of claim 1.
As applied, Huang further discloses wherein a common source-region semiconductor strip is arranged between two adjacent channel semiconductor strips in the height direction in the same column (Fig. 2(f) where it illustrates the shared source on layer 3),
and two drain-region semiconductor strips are arranged on two sides of the two adjacent channel semiconductor strips (Fig. 2(f) where it illustrates the drains of layers 1 and 5 adjacent to channel layers 2 and 4).
Regarding claim 24, Huang and Titus disclose the limitations of claim 1.
As applied, Huang further discloses wherein one interlayer isolation strip is arranged between every two adjacent semiconductor strip structures and another two adjacent semiconductor strip structures in the same semiconductor-strip-structure column in the height direction (Fig. 2(a) where it illustrates the oxide (isolation) layer at the top of the two layer memory stack. Also see col. 1; "It should be mentioned that although only two-layers of vertical flash devices were experimentally demonstrated in this work, our 3D NOR flash has the potential to be stacked with dozens or even hundreds of layers. And the continuous stacking will not degrade the read current, so fast-read still can be realized." It is noted that with the additional stacking indicated, the Huang's oxide isolation layer would necessarily be between every two adjacent memory sub-array layers and analogous to the isolation layer 14a of Fig. 4 in the instant application).
Regarding claim 25, Huang and Titus disclose the limitations of claim 1.
As applied, Huang further discloses wherein in the height direction, a projection of at least a part of each gate strip coincides with a projection of a part of a corresponding channel semiconductor strip in each memory subarray layer on a projection plane, and the projection plane extends along the height direction and the column direction (Fig. 1(a) where it illustrates a gate extending through the semiconductor layers and aligning next to the channel layers. This feature appears to be directed to Fig. 2 and para. 78 of the instant application which are analogous to Huang's channels and gates).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicone Channel; “Huang” – of Record) in view of Titus et al. (US 20220208785; "Titus") and further in view of Lue (US 20160056168).
Regarding claim 26, Huang and Titus combined disclose the limitations of claim 1.
As applied, Huang further discloses or two adjacent columns of gate strips are aligned in the row direction (Fig. 1(a) where it illustrates gates in straight rows).
Huang and Titus combined are silent with respect to staggering the gates.
However, Lue teaches wherein two adjacent columns of gate strips are distributed in a staggered manner in the row direction (Fig. 2 where it illustrates staggered gate rows);
Huang, Titus and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been
obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to
combine the teachings of Huang and Titus combined with the teachings of Lue to stagger the vertical gates memory array. Doing so would allow a larger memory density (Lue para. 55) and help mitigate read disturb events.
Response to Arguments
Applicant's arguments filed January 15, 2026, with respect to amended independent claim 1 have been considered but are moot because the amendment incorporating previously rejected claim 2 in its entirety narrows the scope of claim 1 with respect to the reference previously presented such that the new ground of rejection combines an additional reference, and thereby changes the statutory basis of the rejection. Additionally, the arguments do not challenge any teaching or matter of record relying on only the reference applied in the prior rejection.
Applicant amended withdrawn independent claim 10 and requests rejoinder on pg. 14 of Remarks. This request has been considered, but it is premature because the nonelected claims do not meet the mandatory criteria for rejoinder under MPEP 821.04 as the elected invention is not allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825