DETAILED ACTION
This action is responsive to the amendments filed June 2, 2026. Claims 1, 3-4, 6 and 22 have been amended. Claims 1, 3-15 and 21-26 are pending with claims 10-15 being previously withdrawn from consideration as being directed to non-elected inventions. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on April 15, 2026. This IDS has been considered.
Specification
Applicant's amendment to the title of the invention is acknowledged but not accepted. The currently amended title recites "… AND MANUFACTURE METHOD THEREOF". Only the non-elected claims of the invention are directed toward the manufacture of the memory device. Therefore, the proposed language is still not descriptive or indicative of the invention to which the claims are directed as required. The objection to the title of the invention is maintained.
The following title is suggested: 3D Monolithic Non-Volatile Memory Device with Channel Lead-Out Stepped Structure.
Response to Amendment
Applicant's amendments to correct the base claim of dependent claims 3, 4, and 6 is acknowledged and accepted. The objection to these claims for an invalid base claim is withdrawn.
Applicant's amendment to claim 22 to recite "…tiered along the column direction from top to bottom", is acknowledged and accepted. The indefiniteness rejection for claim 22 has been withdrawn.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-9, and 21-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre- AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claim 1, the claim as currently amended recites (emphasis added): “each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip comprise a body structure and a plurality of protrusions, respectively, the body structure extends along the column direction and is in the shape of a strip, the plurality of protrusions are distributed on both sides of the body structure in two columns, each of two columns comprises a plurality of protrusions spaced apart, and each of the plurality of protrusion extends from the body structure in the row direction toward a corresponding gate strip in a direction deviating from the body structure; and a surface of each of the gate strips near the drain-region semiconductor strip, the channel semiconductor strip, and the source-region semiconductor strip is a curved concave surface.”
The claim is indefinite for the following reasons:
It is unclear what structural features distinguish a “protrusion” from the overall shape of the semiconductor strip. The drawings (particularly Figs. 4 and 11) appear to show continuous rounded or cylindrical structures labeled 15a/15b. A person of ordinary skill in the art cannot determine with reasonable certainty whether a continuous rounded ridge or fin on each side of a central body meets the “plurality of protrusions… spaced apart” limitation, or whether discrete, discontinuous protruding elements are required.
The requirement that the protrusions be “distributed on both sides of the body structure in two columns” is unclear in view of the drawings. Fig. 7, which is cited as illustrating the claimed structure, shows roundedness on only one side of the illustrated feature; the opposite side appears essentially flat. It is therefore unclear whether the claim requires bilateral protrusions with matching concave gate surfaces on both sides, or whether a one-sided rounded interface is sufficient.
The relationship between the recited “curved concave surface” of the gate strips and the protrusions is ambiguous. It is unclear whether each individual protrusion must have a dedicated concave segment on the corresponding gate strip, or whether a generally concave gate surface facing a rounded strip satisfies the language.
The specification (para. 110 – 111) describes semiconductor strips that include a body structure and protrusions that may have an arc or columnar-semicircular convex surface, and further describes a corresponding curved concave gate surface. Nevertheless, when the claim language is read in the light of the specification and the drawings (particularly Figs. 4, 7, and 11), a person of ordinary skill in the art cannot determine with reasonable certainty the metes and bounds of the recited “body structure and a plurality of protrusions… distributed on both sides… spaced apart” and “curved concave surface” limitations, for the reasons set forth above.
For the purpose of applying prior art under MPEP § 2173.06, the examiner interprets the "body structure and plurality of protrusions… distributed on both sides… spaced apart" and "curved concave surface" language as requiring a non-planar, curved interface between the semiconductor strips and the gate strips that increases the effective gate-channel interface area. This interpretation is consistent with the stated purpose of the limitation in the specification (para. 105) and with the overall appearance of the structures shown in Figs. 4, 7, and 11.
Claims 3–9, and 21–26 depend from claim 1 and are likewise indefinite.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-9 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicone Channel; “Huang” – of Record) in view of Cernea et al. (US 20200098779; "Cernea"), and further in view of Shen (US 20220254803).
PNG
media_image1.png
600
677
media_image1.png
Greyscale
PNG
media_image2.png
688
1126
media_image2.png
Greyscale
Regarding independent claim 1, notwithstanding the rejection for indefiniteness above, Huang discloses a memory block, comprising:
A substrate (Fig. 2b. See also col. 1, p. 1875; "The 3D NOR flash was fabricated on a 200 mm Si wafer").
a memory array, arranged on the substrate and comprising a plurality of memory cells distributed in a three-dimensional array, wherein the memory array comprises a plurality of memory subarray layers sequentially stacked along a height direction, and each memory subarray layer comprises a drain-region semiconductor layer, a channel semiconductor layer, and a source-region semiconductor layer stacked along the height direction (Fig. 2a & 2f. See also Abst; "A novel 3D NOR memory array";
each drain-region semiconductor layer comprises a plurality of drain-region semiconductor strips distributed along a row direction, each channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along the row direction, and each source-region semiconductor layer comprises a plurality of source-region semiconductor strips distributed along the row direction (Fig 2a - 2f);
each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip extend along a column direction respectively (Fig. 2. It is noted that this limitation appears to merely define the drain, channel, source layer group as existing in the X-Y plane as illustrated in Huang);
drain-region semiconductor strips, channel semiconductor strips, and source-region semiconductor strips in the same column of the memory subarray layers is defined as a semiconductor-strip-structure column (Fig. 2. It is noted that the term "semiconductor strip structure column" is defined in the specification of the instant application as "a stacked structure 1b" and illustrated in Fig. 3 (Spec. para. 78), which is analogous to the layered stack up in Huang's Fig. 2(a). It is further noted that the structured topology of Huang’s basic 4 transistor building block is identical to the instant application (see Examiner’s Markup above)); and
each well-connection structure corresponds to a corresponding semiconductor-strip-structure column, for electrically connecting the channel semiconductor strips in the corresponding semiconductor-strip-structure column together by using the stepped structure in the corresponding semiconductor-strip-structure column, and then leads out the channel semiconductor strips in the corresponding semiconductor-strip-structure column (Fig. 1(a). It is noted that the well-connection structure as well as other features are indicated in the specification of the instant application to be directed to Fig. 45 (Spec. para. 310) and specifically, as element 111 (filling layer) and 112 (well-connection columns). These are analogous to the column structures in Huang's Fig. 1(a) which are connected to BL1 and BL0 for example. Additional, with respect specifically to the claimed well-lead-out pad of claim 16, the elements BL0 or BL1 of Huang are analogous to the element top 112 as defined in the instant application Spec. para. 319).
wherein at least part of each channel semiconductor strip in each semiconductor-strip-structure column is exposed through the stepped structure thereof (Fig. 2(f), where it illustrates the channel connected to body terminal B1);
While Huang discloses the structure of a stepped contact structure for leading out the connections for the semiconductor layers, an explicit connecting layer covering the tiered structure is not taught.
PNG
media_image3.png
590
872
media_image3.png
Greyscale
However, Cernea teaches a well-lead-out region, comprising a plurality of well-connection structures, wherein each semiconductor-strip-structure column extends to the well-lead-out (Fig. 3(iii). See also para. 23; "One or more portions 108 in each active stack each include at least one “staircase” structure or at least one “reverse staircase” structure. A stair case structure, as well as a reverse staircase structure, allows electrical access to a semiconductor or conductor layer in an active strip", "In FIG. 1a, portions 108 (“staircase portions 108”) are provided in the front and at the back of each active stack. Storage transistors are formed in the portion or portions of the active stack outside of the staircase portion or portions.", "within each staircase portion, a reverse staircase structure is formed by having each active strip extend successively further along the y direction than the active strip below it", It is noted that this element appears to be directed to Fig. 47 of the instant application (well-lead-out region) of which each 'step' is directly analogous to Cernea's portion of 'staircase' as illustrated in Examiner's Markup above.);
in the well-lead-out region, each semiconductor-strip-structure column comprises a stepped structure with a plurality of steps (Fig. 6(iii) where it illustrates a plurality of steps);
and each well-connection structure comprises a connecting layer, the connecting layer covers the stepped structure of the corresponding semiconductor-strip-structure column and connects the channel semiconductor strips in the corresponding semiconductor-strip-structure column together (Fig. 3(iii) where it illustrates connecting layer 551 covering the stepped structure of the semiconductor device. It is noted that Cernea's conductive polysilicon layer 551 electrically connects the channel layer of that active strip to the source (or drain) region of the same active strip. In the NOR architecture disclosed by Cernea, the source regions (or drain regions) of the transistors that share an active strip/column are all commonly connected. Thus, all the channels of the semiconductor strips of the corresponding column are electrically connected together as required by the claim.).
Huang, as modified by Cernea, discloses a three-dimensional NOR memory structure comprising stacked memory subarray layers, each having a drain-region, channel and source-region semiconductor strips with vertical gate structures extending through the layers, and a well-lead-out region, but is silent with respect to the semiconductor regions comprising curved gate structures that increase the effective gate-channel interface area.
However, Shen teaches wherein each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip comprise a body structure and a plurality of protrusions, respectively, the body structure extends along the column direction and is in the shape of a strip, the plurality of protrusions are distributed on both sides of the body structure in two columns, each of two columns comprises a plurality of protrusions spaced apart, and each of the plurality of protrusion extends from the body structure in the row direction toward a corresponding gate strip in a direction deviating from the body structure (Figs. 1A and 1B. See also para. 35; "Thin-film channel layer 401 therefore forms a concave channel region at each of the word lines 911-918, which extends around the perimeter of the vertical opening.", "The memory cells formed thereby have a curved and confined channel layer, between the adjacent layers of insulating material". Further see para 28; "the layers of word line material have recessed inside surfaces, recessed relative to inside surfaces facing the opening of the adjacent ones of the alternating layers of insulating material);
and a surface of each of the gate strips near the drain-region semiconductor strip, the channel semiconductor strip, and the source-region semiconductor strip is a curved concave surface (para. 34; "This concave channel region over the recessed inside surfaces of the layers of word line material can be continuous around the perimeter of the vertical opening, forming a horizontal channel." Further, see Abstr. "One of the layers of insulating material and layers of word line material have recessed inside surfaces facing the opening.", "A semiconductor channel layer is disposed on the data storage structures around a perimeter of the vertical opening". It is also noted that Shen states the purpose for the curved channel structure: para. 34; "This structure can result in better isolation between the layers of memory cells and less disturbance of neighboring cells when activating a given cell within the stack" which is analogous to the instant application and Shen's rationale appears throughout the reference for both the concave and convex embodiments.).
Huang, Cernea and Shen are from the same field of endeavor as applicants’ invention being directed to 3D memory devices. Under the interpretation of the limitations of the claim pursuant to MPEP § 2173.06 in the indefiniteness rejection above (i.e., a non-planar, curved interface between the semiconductor strips and the gate strips that increases the effective gate-channel interface area) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor stack/strips with stepped well-lead-out region with connecting layer of Huang and Cernea with the curved (concave) channel geometry taught by Shen. Doing so would improve semiconductor device density. The modification is nothing more than the application of a known performance-enhancing curved interface (Shen) to a known 3D NOR stacked structure (Huang/Cernea) to achieve a predictable result.
Regarding claim 3, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses each step comprises a first surface and a second surface, the first surface is parallel to the substrate, and the second surface is perpendicular to the substrate (Fig. 2(c), where it illustrates the bottom of the body contact hole that is parallel to the substrate);
the first surface of each step is configured to expose at least part of a corresponding channel semiconductor strip in the corresponding semiconductor-strip-structure column and the second surface of each step is covered by an insulating dielectric, to avoid exposing the drain-region semiconductor strips and the source-region semiconductor strips in the corresponding semiconductor-strip-structure column (Fig. 2(c), where it illustrates the side of the body contact hole which is perpendicular to the substrate and is covered by an oxide spacer (insulating));
the connecting layer is configured to cover the stepped structure, contact the part of the corresponding channel semiconductor strip exposed through the first surface of each step, and be insulated from the drain-region semiconductor strips and the source-region semiconductor strips in the corresponding semiconductor-strip-structure column through the insulating dielectric (Fig. 2(d) and 2(e), where it illustrates the tungsten plug connecting layer inside the oxide insulating layer and protruding through the top (insulating dielectric) oxide layer).
Regarding claim 4, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein the connecting layer.
Huang does not expressly indicate the material of the connecting layer as polycrystalline silicon or the use of other materials.
However, Huang’s Fig. 2(d) illustrates the tungsten plugs forming the connecting layer.
In the field of 3D memory device manufacturing, it is well understood that there are many possible electrically conducting materials which may be used to form connecting layers of which polycrystalline silicon and tungsten are both common material variants exhibiting common similar deposition and conduction suitability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a connecting layer using tungsten instead of polysilicon, because tungsten and polysilicon are obvious variants due to their analogous material characteristics with respect to memory device manufacturing.
Regarding claim 5, Huang, Cernea and Shen combined disclose the limitations of claim 4.
As applied, Cernea teaches a doping type of the connecting layer is the same as that of the channel semiconductor strip and is opposite to that of the drain-region semiconductor strip and the source-region semiconductor strip (Fig. 4. See also para. 59; "A conformal conductive polysilicon film 601 (e.g., 40 nm thick) is then deposited over the step. Polysilicon film 601 may have a boron dopant concentration of around 1.0×10.sup.19 cm.sup.−3-5.0×10.sup.19 cm.sup.−3").
Regarding claim 6, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses each well-connection structure further comprises a connection-improvement layer arranged on the connecting layer, and the connection-improvement layer is a metal-silicide layer (Fig. 2(c), Silicide connection improvement layer at the bottom of the connection layer hole).
Regarding claim 7, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip are single-crystal semiconductor strips respectively (Abstr. "To obtain single-crystal silicon channel for 3D NOR, 1) vertical flash devices were presented, 2) a stack with multiple doped epitaxial Si layers was used for making the vertical devices." It is noted that the single-crystal silicon layers comprise drain, channel and source strips as illustrated in fig. 2 and analogous to the layers in the instant application).
Regarding claim 8, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses along the height direction, two adjacent memory subarray layers comprise one drain-region semiconductor layer, one channel semiconductor layer, one source-region semiconductor layer, another channel semiconductor layer, and another drain-region semiconductor layer sequentially stacked to share the same source-region semiconductor layer (Fig. 2(a); and
an interlayer isolation layer is arranged between every two adjacent memory subarray layers and another two adjacent memory subarray layers to isolate every two adjacent memory subarray layers from another two adjacent memory subarray layers (Fig. 2(a) where it illustrates the oxide (isolation) layer at the top of the two layer memory stack. Also see col. 1; "It should be mentioned that although only two-layers of vertical flash devices were experimentally demonstrated in this work, our 3D NOR flash has the potential to be stacked with dozens or even hundreds of layers. And the continuous stacking will not degrade the read current, so fast-read still can be realized." It is noted that with the additional stacking indicated, the Huang's oxide isolation layer would necessarily be between every two adjacent memory sub-array layers and analogous to the isolation layer 14a of Fig. 4 in the instant application).
Regarding claim 9, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses an interlayer-dielectric layer, covering the memory array and the well-lead-out region, wherein, in the well-lead-out region, the interlayer-dielectric layer has at least one lead-out hole corresponding to each well-connection structure, a connecting column is arranged in the lead-out hole, one end of the connecting column is connected to a corresponding well-connection structure, and the other end of the connecting column is exposed outside the interlayer-dielectric layer to serve as a lead-out pad (Fig. 1).
Regarding claim 21, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Cernea further discloses each drain-region semiconductor strip and each source-region semiconductor strip are semiconductor strips with a first doping type, and each channel semiconductor strip is a semiconductor strip with a second doping type (Fig. 3(i) where it illustrates source 523 and drain 521 as N+ Poly and body (channel) 403 as P+ Poly. It is well understood in the art that the doping of the source and drain of the transistors is opposite polarity of the doping of the channel).
Regarding claim 22, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Cernea further discloses wherein the steps comprised in the stepped structure are tiered along the column direction from top to bottom (Fig. 4(i)).
Regarding claim 23, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein a common source-region semiconductor strip is arranged between two adjacent channel semiconductor strips in the height direction in the same column (Fig. 2(f) where it illustrates the shared source on layer 3),
and two drain-region semiconductor strips are arranged on two sides of the two adjacent channel semiconductor strips (Fig. 2(f) where it illustrates the drains of layers 1 and 5 adjacent to channel layers 2 and 4).
Regarding claim 24, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein one interlayer isolation strip is arranged between every two adjacent semiconductor strip structures and another two adjacent semiconductor strip structures in the same semiconductor-strip-structure column in the height direction (Fig. 2(a) where it illustrates the oxide (isolation) layer at the top of the two layer memory stack. Also see col. 1; "It should be mentioned that although only two-layers of vertical flash devices were experimentally demonstrated in this work, our 3D NOR flash has the potential to be stacked with dozens or even hundreds of layers. And the continuous stacking will not degrade the read current, so fast-read still can be realized." It is noted that with the additional stacking indicated, the Huang's oxide isolation layer would necessarily be between every two adjacent memory sub-array layers and analogous to the isolation layer 14a of Fig. 4 in the instant application).
Regarding claim 25, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein in the height direction, a projection of at least a part of each gate strip coincides with a projection of a part of a corresponding channel semiconductor strip in each memory subarray layer on a projection plane, and the projection plane extends along the height direction and the column direction (Fig. 1(a) where it illustrates a gate extending through the semiconductor layers and aligning next to the channel layers. This feature appears to be directed to Fig. 2 and para. 78 of the instant application which are analogous to Huang's channels and gates).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicone Channel; “Huang” – of Record) in view of Cernea et al. (US 20200098779), and further in view of Shen (US 20220254803), and further in view of Lue (US 20160056168).
Regarding claim 26, Huang, Cernea and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses or two adjacent columns of gate strips are aligned in the row direction (Fig. 1(a) where it illustrates gates in straight rows).
Huang, Cernea and Shen combined combined are silent with respect to staggering the gates.
However, Lue teaches wherein two adjacent columns of gate strips are distributed in a staggered manner in the row direction (Fig. 2 where it illustrates staggered gate rows);
Huang, Cernea, Shen and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device of Huang (as modified by Cernea and Shen) with the teachings of Lue to stagger the vertical gates memory array. Doing so would allow a larger memory density (Lue para. 55) and help mitigate read disturb events.
Response to Arguments
Applicant's arguments filed June 2, 2026, have been considered but are unpersuasive with regard to overcoming the rejections of record as modified herein.
Applicant contends in Remarks that the obviousness rejection of claim 1 is improper due to the cited references failing to disclose either alone or in combination, three groups distinguishing technical features” (Features A, B, and C).
Feature A (body structure, protrusions, curved concave gate surface)
Applicant argues that the previously applied references fail to teach the newly added limitations requiring that each drain-region, channel, and source-region semiconductor strip comprises a body structure and a plurality of protrusions distributed on both sides in two columns and spaced apart, and that a surface of each gate strip is a curved concave surface.
The newly added language is indefinite under 35 U.S.C. § 112(b) for the reasons set forth in the rejection above (ambiguity of “body structure and a plurality of protrusions… distributed on both sides… spaced apart,” and the drawings, particularly FIG. 7, fail to clearly depict the claimed bilateral spaced-apart protrusions and matching curved concave surfaces).
Under the broadest reasonable interpretation consistent with the specification (MPEP § 2173.06), the language is understood to require a non-planar, curved interface between the semiconductor strips and the gate strips that increases interfacial area. Under that interpretation, the limitations are taught by Huang in view of the newly applied reference, Shen (see the § 103 rejection of claim 1). Applicant’s argument is therefore not persuasive.
Feature B (well-lead-out region, stepped structure, connecting layer)
Applicant argues that a previously applied reference (Titus) retro-stepped dielectric material portion 65 is an insulating fill and therefore cannot serve as the claimed connecting layer that electrically connects the channel semiconductor strips of a semiconductor-strip-structure column together, and that Titus’s peripheral staircase is a conventional word-line contact structure rather than the claimed well-lead-out region.
The rejection of claim 1 has been modified. Titus is no longer relied upon for the connecting-layer limitation. The combination of Huang and Cernea is now applied.
Cernea expressly teaches staircase portions formed at the ends of the active strips of a 3D NOR array for the purpose of making electrical connection to the semiconductor layers (including body/channel layers) within those strips (Cernea para. 23; FIGS. 1a, 3(iii), 4). Cernea further teaches a conductive layer (conformally deposited conductive polysilicon layer 551) formed over the stepped surfaces of the active strips (FIG. 3(iii)). That conductive structure electrically connects the body/channel layer of each active strip to the source (or drain) of the same strip. In the NOR architecture the sources (or drains) of a column are already commonly connected; shorting each channel strip to the common source/drain node therefore electrically connects the channel semiconductor strips of the column together. The claim language does not require a direct exclusive path or a continuous multi-step blanket layer.
Applicant’s arguments directed to the specific deficiencies of Titus’s dielectric staircase are therefore moot as to the current rejection.
Feature C (semiconductor-strip-structure columns)
Applicant argues that Huang discloses only continuous planar epitaxial layers and that Titus discloses a conventional alternating insulator/word-line stack, neither of which constitutes the claimed semiconductor-strip-structure columns.
This argument has been considered and is not persuasive. Huang’s topology (FIG. 1(b) and related figures) depicts independent transistors. For those devices to function as independent cells (which is evidenced by Huang's experimental results), insulating material must separate adjacent transistors. Under that construction, Huang’s structure is effectively analogous to the claimed semiconductor-strip-structure columns—stacked drain/channel/source regions that are laterally isolated from neighboring devices, forming discrete vertical columns of active strips. This is the same construction applied in the related co-pending application and is consistent with the broadest reasonable interpretation of the claim language.
For at least these reasons, the rejection of claim 1 is maintained and updated as set forth above.
Applicant also amended withdrawn independent claim 10 and requests rejoinder of claims 10-15 on pg. 24 of Remarks. This request has been considered, but it is premature because the nonelected claims do not meet the mandatory criteria for rejoinder under MPEP 821.04 as the elected invention is not allowable.
Lastly, applicant's arguments concerning the dependent claims are essentially that those claims stand or fall with claim 1. Because claim 1 remains rejected, the dependent claims are likewise rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/James S. Wells/Examiner, Art Unit 2825 /Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
Prosecution Insights