Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to application 18/528879 filed on 12/05/23.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsutsui et al. (U.S Pub. 2023/0307447).
As to claim 1 the prior art teaches a semiconductor structure comprising:
a plurality of semiconductor devices, comprising a first semiconductor device and a second semiconductor device (see fig 1-4 paragraph 0023-0027);
a first contact contacting: (i) the first semiconductor device and (ii) the second semiconductor device (see fig 1-4 paragraph 0025-0029);
a second contact contacting the first semiconductor device (see fig 1-5 paragraph 0041-0045);
and a third contact contacting the second semiconductor device (see fig 1-5 paragraph 0044-0049).
As to claim 2 the prior art teaches further comprising a power delivery network electrically connected to: (i) the second contact and (ii) the third contact (see fig 3-7 paragraph 0037-0039).
As to claim 3 the prior art teaches further comprising: a first power delivery network electrically connected to the second contact; and a second power delivery network electrically connected to the third contact (see fig 3-6 paragraph 0043-0047).
As to claim 4 the prior art teaches wherein the second contact contacts the first semiconductor device in a first direction; and the third contact contacts the second semiconductor device in the first direction (see fig 5-8 paragraph 0052-0056).
As to claim 5 the prior art teaches wherein the first contact contacts the first semiconductor device and the second semiconductor device in a second direction (see fig 5-8 paragraph 0055-0059).
As to claim 6 the prior art teaches wherein the second contact and the third contact are each backside contacts (see fig 6-9 paragraph 0058-0062).
As to claim 7, the prior art teaches wherein the first contact is a frontside contact (see fig 6-8 paragraph 0060-0064).
As to claim 8 the prior art teaches wherein the second contact and the third contact are each frontside contacts (see fig 8-10 paragraph 0063-0066).
As to claim 9 the prior art teaches wherein the first contact is a backside contact (see fig 3-6 paragraph 0039-0040).
As to claim 10 the prior art teaches wherein the first contact is electrically connected to a third semiconductor device through a power railb(see fig 3-6 paragraph 0041-0043).
As to claim 11 the prior art teaches wherein: the second semiconductor device is in an off state (see fig 5-9 paragraph 0050-0053);
and electric current passes from the power delivery network, through the third contact, the second semiconductor device, and the first contact, to the first semiconductor device (see fig 5-9 paragraph 0052-0055).
As to claim 12, the prior art teaches wherein electric current passes from the power delivery network, through the second contact, to the first semiconductor device (see fig 3-6 paragraph 0046-0050).
As to claim 13 the prior art teaches a method of forming a semiconductor structure, the method comprising:
forming a plurality of semiconductor devices, comprising a first semiconductor device and a second semiconductor device (see fig 1-4 paragraph 0023-0027);
forming a first contact, wherein the first contact contacts: (i) the first semiconductor device and (ii) the second semiconductor device (see fig 1-4 paragraph 0025-0029);
and forming a second contact and a third contact (see fig 1-5 paragraph 0041-0045), wherein the second contact contacts the first semiconductor device and the third contact contacts the second semiconductor device (see fig 1-5 paragraph 0044-0049).
As to claim 14 the prior art teaches further comprising: forming a backside back end of line (BEOL) interconnect (see fig 3-6 paragraph 0038-0040).
As to claim 15, the prior art teaches further comprising: forming a frontside middle of line (MOL) and back end of line (BEOL) interconnect (see fig 3-6 paragraph 0039-0042).
As to claim 16 the prior art teaches further comprising flipping the semiconductor structure subsequent to forming the first contact and prior to forming the second contact and the third contact (see fig 4-7 paragraph 0048-0051).
As to claim 17 the prior art teaches further comprising flipping the semiconductor structure subsequent to forming the second contact and the third contact and prior to forming the first contact (see fig 4-7 paragraph 0050-0053).
As to claim 18, the prior art teaches a method comprising:
providing a semiconductor structure comprising: a plurality of semiconductor devices (see fig 1-4 paragraph 0023-0025);
a first contact contacting each of the plurality of semiconductor devices (see fig 1-4 paragraph 0023-0027);
a second contact contacting a first semiconductor device of the plurality of semiconductor devices (see fig 1-4 paragraph 0025-0029);
and a third contact contacting a second semiconductor device of the plurality of semiconductor devices (see fig 1-5 paragraph 0041-0045);
and providing, by a power delivery network (see fig 1-5 paragraph 0037-0039), electric current through the second contact and the third contact (see fig 1-5 paragraph 0044-0049).
As to claim 19 the prior art teaches further comprising: providing additional electric current to the second semiconductor device by placing the first semiconductor device in an off state such that electric current passes through the first semiconductor device and the first contact from the second contact (see fig 1-5 paragraph 0037-0042).
As to claim 20, the prior art teaches further comprising: providing additional electric current to the first semiconductor device by placing the second semiconductor device in an off state such that electric current passes through the second semiconductor device and the first contact from the third contact (see fig 1-5 paragraph 0048-0053).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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