DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-18, in the reply filed on 03/25/2026 is acknowledged.
Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/25/2026.
Claim Objections
Claim 11 is objected to because of the following informalities: abbreviations “pFET” and “nFET” are recited but without further description. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Engel (US 2023/0369222).
Regarding claim 10, Engel discloses, in FIG. 4 and in related text, a semiconductor integrated circuit (IC) device comprising:
a first transistor (204 on the left) and a second transistor (204 on the right);
the first transistor (204 on the left) comprising a first source/drain (S/D) region (214B on the left) and a first backside contact connected to and below the first S/D region, the first backside contact comprising a first inline region (408 on the left) and a first extension region (406 on the left) extending from the first inline region horizontally away from the second transistor; and
the second transistor (204 on the right) comprising a second S/D region (214B on the right) and a second backside contact connected to and below the second S/D region, the second backside contact comprising a second inline region (408 on the right) and a second extension region (406 on the right) extending from the second inline region horizontally away from the first transistor (see Engel, [0037]-[0039]).
Regarding claim 14, Engel discloses the device of claim 10.
Engel discloses wherein the first inline region (408 on the left) is substantially inline with and below the first S/D region (214B on the left) and wherein the second inline region (408 on the right) is substantially inline with and below the second S/D region (214B on the right) (see Engel, FIG. 4).
Claims 10-11 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 2023/0223455).
Regarding claim 10, Liaw discloses, in FIGS. 5A-5D and in related text, a semiconductor integrated circuit (IC) device comprising:
a first transistor (PT1) and a second transistor (NT3);
the first transistor (PT1) comprising a first source/drain (S/D) region (418) and a first backside contact connected to and below the first S/D region, the first backside contact comprising a first inline region (602-5) and a first extension region (702-5) extending from the first inline region horizontally away from the second transistor; and
the second transistor (NT3) comprising a second S/D region (418) and a second backside contact connected to and below the second S/D region, the second backside contact comprising a second inline region (602-1) and a second extension region (702-1) extending from the second inline region horizontally away from the first transistor (see Liaw, [0057], [0077], [0082]-[0083]).
Regarding claim 11, Liaw discloses the device of claim 10.
Liaw discloses wherein the first transistor (PT1) is a pFET and the second transistor (NT3) is an nFET (see Liaw, [0057]).
Regarding claim 13, Liaw discloses the device of claim 10.
Liaw discloses a backside back end of line (BEOL) network comprising a first backside wire (608-2, Vdd) below and connected to the first extension region (702-5) and a second backside wire (608-1, Vss) below and connected to the second extension region (702-1) (see Liaw, FIGS. 5A-5D, [0075], [0077], [0083]).
Regarding claim 14, Liaw discloses the device of claim 10.
Liaw discloses wherein the first inline region (602-5) is substantially inline with and below the first S/D region (418) and wherein the second inline region (602-1) is substantially inline with and below the second S/D region (418) (see Liaw, FIGS. 5A-5D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Lee (US 2024/0105615).
Regarding claim 17, Liaw discloses the device of claim 10.
Liaw discloses wherein the first transistor comprises the first S/D region and the first inline region and wherein the second transistor comprises the second S/D region and the second inline region (see discussion on claim 10 above).
Liaw does not explicitly disclose wherein the first transistor comprises a first etch stop between the first S/D region and the first inline region and wherein the second transistor comprises a second etch stop between the second S/D region and the second inline region.
Lee teaches wherein a transistor comprises an etch stop (181) between a S/D (SD2) region and an inline region (BCA1) (see Lee, FIG. 35A, [0166]). Therefore, Lee together with Liaw teaches wherein the first transistor comprises a first etch stop between the first S/D region and the first inline region and wherein the second transistor comprises a second etch stop between the second S/D region and the second inline region.
Liaw and Lee are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw with the features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Liaw to include wherein the first transistor comprises a first etch stop between the first S/D region and the first inline region and wherein the second transistor comprises a second etch stop between the second S/D region and the second inline region, as taught by Lee, to control contact resistance (see Lee, [0166]).
Allowable Subject Matter
Claims 1-9 are allowed.
Claims 12, 15-16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, Morrow (US 2021/0111115), discloses a semiconductor integrated circuit (IC) device comprising: a backside back end of line (BEOL) network comprising a backside wire; a first source/drain (S/D) region and a replacement placeholder below the first S/D region; and a second S/D region and a backside contact connected to and below the second S/D region, the backside contact comprising an extension region between the backside wire and the replacement placeholder. See Morrow, FIGS. 9B and 14; paragraphs [0040]-[0041] and [0046]. The prior art of records, individually or in combination, do not disclose nor teach “a first transistor comprising a first source/drain (S/D) region; a second transistor comprising a second S/D region” in combination with other limitations as recited in claim 1.
The prior art of records, individually or in combination, do not disclose nor teach “wherein an interlayer dielectric (ILD) is between sidewall(s) of the first S/D region and sidewall(s) of the second S/D region” in combination with other limitations as recited in claim 12.
The prior art of records, individually or in combination, do not disclose nor teach “wherein a pitch between the first backside wire and the second backside wire is greater than a pitch between the first S/D region and the second S/D region” in combination with other limitations as recited in claim 15.
The prior art of records, individually or in combination, do not disclose nor teach “wherein a pitch between the first backside wire and the second backside wire is greater than a pitch between the first inline region and the second inline region” in combination with other limitations as recited in claim 16.
The prior art of records, individually or in combination, do not disclose nor teach “wherein a shallow trench isolation (STI) region is between the first inline region and the second inline region.” in combination with other limitations as recited in claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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