CTNF 18/528,917 CTNF 87597 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Election/Restrictions 1 . Applicant's election, with traverse, of claims 1-14 in the “Response to Restriction Requirement” filed on 03/26/2026 is acknowledged and entered by the Examiner. Applicant’s arguments, in “Applicant Arguments/Remarks Made” with the reply “Response to Election / Restriction Filed” filed on 03/26/2026”, see “Accordingly, it is respectively asserted that, as Figures 9A-9B are simply showing an intermediary step on the way to forming the structure depicted in Figures 10A-10B, and that all elements disclosed in claims 1-14 are depicted in Figures 10A-10B, the separate species categorization is incorrect and no search or examination burden is present” (remarks on pages 2-3) have been fully considered. The examiner has found the Applicant’s arguments to be persuasive. Therefore, the species restriction requirement between claims 1-8 and 9-14 as set forth in the Office action mailed on 01/28/2026 is hereby withdrawn. In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a combination or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler , 443 F.2d 122, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01. This office action consider claims 1-20 pending for prosecution, wherein claims 15-20 are withdrawn from further consideration, and claims 1-14 are presented for examination. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 2. Claims 11-13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding Claim 11, the instant claim recites limitations in view of the parent device claim 9, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “wherein the low-power nanosheet gate-all-around field-effect transistor has the source/drain contacting at least one channel of the plurality of channels” (Claim 11; emphasis added). The claim is indefinite because of the following: i) The claim is indefinite because “wherein the low-power nanosheet gate-all-around field-effect transistor has the source/drain contacting at least one channel of the plurality of channels” (Claim 11) is ambiguous and unclear whether the recitation of “ the source/drain ” in line 2 of claim 11 refers to the recitation of “a source/drain” in line 4 of claim 9. The reason for the confusion is as “a source/drain” in line 4 of claim 9 is directed to being part of a high-performance nanosheet gate-all-around field-effect transistor, while “ the source/drain ” in line 2 of claim 11 refers to being part of the low-power nanosheet gate-all-around field-effect transistor. Therefore, the limitation of “wherein the low-power nanosheet gate-all-around field-effect transistor has the source/drain contacting at least one channel of the plurality of channels” (Claim 11) is indefinite and unclear. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention. As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claim, it would not be proper for the examiner to reject such a claim on the basis of prior art. See MPEP § 706 and MPEP § 2173.II (second) wherein In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims. Regarding Claim 12, the instant claim recites limitations in view of the parent device claim 9, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “wherein the high-performance nanosheet gate-all-around field-effect transistor includes a backside contact contacting the source/drain, wherein the backside contact contacts a backside power rail, a bottom interlayer dielectric, a bottom dielectric isolation, and the source/drain” (Claim 12; emphasis added). The claim is indefinite because of the following: i) The claim is indefinite because “wherein the high-performance nanosheet gate-all-around field-effect transistor includes a backside contact contacting the source/drain, wherein the backside contact contacts a backside power rail, a bottom interlayer dielectric, a bottom dielectric isolation, and the source/drain” (Claim 12) is ambiguous and unclear whether the recitation of “ a backside contact ” in line 2 of claim 12 and “ the backside contact ” in line 3 of claim 12 refers to the recitation of “a backside contact” in line 2 of claim 9. The reason for the confusion is there are two references to “a backside contact” (see line 2 of claim 9, and see line 2 of claim 12) and one reference to “the backside contact” (see line 3 of claim 12). Thus, there is confusion to the backside contacts and what they are in reference to. Therefore, the limitation of “wherein the high-performance nanosheet gate-all-around field-effect transistor includes a backside contact contacting the source/drain, wherein the backside contact contacts a backside power rail, a bottom interlayer dielectric, a bottom dielectric isolation, and the source/drain” (Claim 12) is indefinite and unclear. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention. As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claim, it would not be proper for the examiner to reject such a claim on the basis of prior art. See MPEP § 706 and MPEP § 2173.II (second) wherein In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims. Regarding Claim 13, it is rejected under 112(b) because of its dependency status from claim 12. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Notes : when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as ( 100 ; Fig 3A; [0063]) = (element 100 ; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 07-15 AIA 3. Claim s 1-14 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Huang et al. (US 20220028786 A1; hereinafter Huang ) . Regarding claim 1 , Huang teaches a semiconductor device ( see the entire document, specifically Fig. 1+; [0001+], and as cited below ), comprising: a dielectric material ( 260 ; Fig. 21B; see [0035-0038]) contacting a backside contact ( 262 ; Fig. 21B; see [0037-0040]) and at least one channel ({ 206, 210B }; Fig. 21B in view of Figs. 1-8; see [0017, 0019]; where layers 206 and 210 are semiconductor layers that alternate; thus, it is construed that layers 206 and 210 are channels layers of a stack, where 206 is the bottom channel layer of the stack comprising of 206, 201B ) of a nanosheet ({ 206, 210B }; Fig. 21B in view of Figs. 1-8; see [0017, 0019]) field-effect transistor, wherein the dielectric material ( 260 ; Fig. 21B; see [0035-0038]) is between the at least one channel ({ 206, 210B }; Fig. 21B in view of Figs. 1-8; see [0017]) and the backside contact ( 262 ; Fig. 21B; see [0037-0040]). Regarding claim 2 , Huang teaches all of the features of claim 1. Huang further teaches wherein the backside contact ( 262 ; Fig. 21B; see [0037-0040]) extends above a top surface (top surface of { 206 }; Fig. 21B in view of Figs. 1-8; see [0017]) of a bottom channel ({ 206, 210B }; Fig. 21B in view of Figs. 1-8; see [0017, 0019]; where layers 206 and 210 are semiconductor layers that alternate; thus, it is construed that layers 206 and 210 are channels layers of a stack, where 206 is the bottom channel layer of the stack comprising of 206, 201B ) of the field-effect transistor. Regarding claim 3 , Huang teaches all of the features of claim 1. Huang further teaches wherein the backside contact ( 262 ; Fig. 21B; see [0037-0040]) is directly under and contacts a source/drain ( 240 ; Fig. 21B; see [0039-0040]). Regarding claim 4 , Huang teaches all of the features of claim 3. Huang further teaches wherein the source/drain ( 240 ; Fig. 21B; see [0039-0040]) directly contacts each channel ({ 210B }; Fig. 21B in view of Figs. 1-8; see [0017]) that is not electrically isolated from the backside contact ( 262 ; Fig. 21B; see [0037-0040]) by the dielectric material ( 260 ; Fig. 21B; see [0035-0038]). Regarding claim 5 , Huang teaches all of the features of claim 3. Huang further teaches wherein the source/drain ( 240 ; Fig. 21B; see [0039-0040]) has vertical sidewalls and a rounded bottom surface (see Fig. 21B), wherein the rounded bottom surface has an upside-down u-shape (see Fig. 21B). Regarding claim 6 , Huang teaches all of the features of claim 1. Huang further teaches wherein the backside contact ( 262 ; Fig. 21B; see [0037-0040]) resides on a backside power rails ( 270 ; Fig. 21B; see [0040]) above one or more layers of backside interconnect wiring ( 280 ; Fig. 21B; see [0040]). Regarding claim 7 , Huang teaches all of the features of claim 1. Huang further teaches wherein the semiconductor device ( 200 ; Fig. 21B; see [0001, 0012, 0040]) is a (see below for “ low - power ”) nanosheet gate-all-around field-effect transistor (Fig. 21B; see [0001, 0012, 0040]). In regards to “ wherein the semiconductor device is a low-power nanosheet gate-all-around field-effect transistor” , as per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Huang teaches the structure of claims 1 and 7 as detailed above. Thus, Huang teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Regarding claim 8 , Huang teaches all of the features of claim 1. Huang further teaches wherein the dielectric material ( 260 ; Fig. 21B; see [0035-0038]) contacts sidewalls of the backside contact ( 262 ; Fig. 21B; see [0037-0040]), sidewalls of at least a bottom channel ({ 206 }; Fig. 21B in view of Figs. 1-8; see [0017]), a top surface of at least of a bottom inner spacer ({ 256 }; Fig. 21B in view of Figs. 1-8; see [0037]) of a gate, and a bottom surface of at least an inner spacer ({ 226 }; Fig. 21B in view of Figs. 1-8; see [0039]) above the at least bottom inner spacer ({ 256 }; Fig. 21B in view of Figs. 1-8; see [0037]) of the gate. Regarding claim 9 , Huang teaches a semiconductor structure of a semiconductor chip ( see the entire document, specifically Fig. 1+; [0001+], and as cited below ), comprising: a (see below for “ low - power ”) nanosheet gate-all-around field-effect transistor (Fig. 21B; see [0001, 0012, 0040]) with a backside contact ( 262 ; Fig. 21B; see [0037-0040]) electrically isolated from at least one channel ({ 206, 210B }; Fig. 21B in view of Figs. 1-8; see [0017, 0019]; where layers 206 and 210 are semiconductor layers that alternate; thus, it is construed that layers 206 and 210 are channels layers of a stack, where 206 is the bottom channel layer of the stack comprising of 206, 201B ) of a plurality of nanosheet channels ({ 206, 210B }; Fig. 21B in view of Figs. 1-8; see [0017, 0019]); and a (see below for “ high-performance ”) nanosheet gate-all-around field-effect transistor (Fig. 21B; see [0001, 0012, 0040]) with a source/drain ( 240D ; Fig. 21B; see [0017]) contacting each of the plurality of nanosheet channels ({ 206, 210B }; Fig. 21B in view of Figs. 1-8; see [0017, 0019]). In regards to “ a low-power nanosheet gate-all-around field-effect transistor” , as per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Huang teaches the structure of claim 9 as detailed above. Thus, Huang teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. In regards to “ a high-performance nanosheet gate-all-around field-effect transistor” , as per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Huang teaches the structure of claim 9 as detailed above. Thus, Huang teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Regarding claim 10 , Huang teaches all of the features of claim 9. Huang further teaches wherein the low-power nanosheet gate-all-around field semiconductor device (Fig. 21B; see [0001, 0012, 0040]) includes a dielectric material ( 260 ; Fig. 21B; see [0035-0038]) between at least one bottom channel ({ 206, 210B }; Fig. 21B in view of Figs. 1-8; see [0017, 0019]; where layers 206 and 210 are semiconductor layers that alternate; thus, it is construed that layers 206 and 210 are channels layers of a stack, where 206 is the bottom channel layer of the stack comprising of 206, 201B ) and the backside contact ( 262 ; Fig. 21B; see [0037-0040]), and wherein the backside contact ( 262 ; Fig. 21B; see [0037-0040]) has a rounded top surface contacting a source/drain ( 240S ; Fig. 21B; see [0039-0040]) of the low-power nanosheet gate-all-around field-effect (Fig. 21B; see [0001, 0012, 0040]). Regarding claim 11 , Huang teaches all of the features of claim 9. Huang further teaches wherein the low-power nanosheet gate-all-around field-effect has the source/drain contacting at least one channel of the plurality of channels ( see section 2 above; 112(b) rejection ). Regarding claim 12 , Huang teaches all of the features of claim 9. Huang further teaches wherein the high-performance nanosheet gate-all-around field-effect transistor includes a backside contact contacting the source/drain, wherein the backside contact contacts a backside power rail, a bottom interlayer dielectric, a bottom dielectric isolation, and the source/drain ( see section 2 above; 112(b) rejection ). Regarding claim 13 , Huang teaches all of the features of claim 12. Huang further teaches wherein the source/drain contacts each channel of the high-performance nanosheet gate-all-around field-effect transistor ( see section 2 above; 112(b) rejection ). Regarding claim 14 , Huang teaches all of the features of claim 9. Huang further teaches wherein the low-power nanosheet gate-all-around field-effect transistor (Fig. 21B; see [0001, 0012, 0040]) and the high-performance nanosheet gate-all-around field-effect transistor (Fig. 21B; see [0001, 0012, 0040]) reside on a backside power rail ( 270 ; Fig. 21B; see [0040]) in a semiconductor chip (Fig. 21B; see [0040] in view of [0013]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /OMAR F MOJADDEDI/Examiner, Art Unit 2898 Application/Control Number: 18/528,917 Page 2 Art Unit: 2898 Application/Control Number: 18/528,917 Page 3 Art Unit: 2898 Application/Control Number: 18/528,917 Page 4 Art Unit: 2898 Application/Control Number: 18/528,917 Page 5 Art Unit: 2898 Application/Control Number: 18/528,917 Page 6 Art Unit: 2898 Application/Control Number: 18/528,917 Page 7 Art Unit: 2898 Application/Control Number: 18/528,917 Page 8 Art Unit: 2898 Application/Control Number: 18/528,917 Page 9 Art Unit: 2898 Application/Control Number: 18/528,917 Page 10 Art Unit: 2898 Application/Control Number: 18/528,917 Page 11 Art Unit: 2898 Application/Control Number: 18/528,917 Page 12 Art Unit: 2898 Application/Control Number: 18/528,917 Page 13 Art Unit: 2898
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