DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
Specification ¶[0034]: “…provided inside the delay locked loop to so that …” Word ‘to’ incorrect.
Specification ¶[0044]: “…or the same signal waveform refer to be within the allowable error range.” Unclear language.
Specification ¶[0045]: “…one delayed target clock signal only include a second target clock signal.” Improper subject/verb agreement.
Specification ¶[0045]: " Thais, the first target clock signal …” Misspelled word.
Appropriate correction is required.
Claim Objections
Claim 11 depends from Claim 9 but is separated from it by Claim 10, which does not itself depend from Claim 9. A series of singular dependent claims is permissible in which a dependent claim refers to a preceding claim which, in turn, refers to another preceding claim.
A claim which depends from a dependent claim should not be separated by any claim which does not also depend from said dependent claim. It should be kept in mind that a dependent claim may refer to any preceding independent claim. In general, applicant's sequence will not be changed. See MPEP § 608.01(n).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 14, and 17-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 7,872,924 B2 to Yantao Ma (hereafter Ma).
Regarding Claim 1, Ma discloses a delay locked loop, comprising:
a pre-processing module,
configured to receive an initial clock signal (A pre-processing circuit including complementary clock signals 610 and 630 and input buffer 635: Ma, Figure 6 and col.10:45-46),
pre-process the initial clock signal and output a first clock signal (Input buffer 635 out putting a first clock signal ClkRef: Ma, Figure 6 and col.10:53-54);
a first variable delay line (Variable delay line 640: Ma, Figure 6),
configured to receive the first clock signal (Delay line 640 coupled to ClkRef: Ma, Figure 6 and col.10:53-54),
adjust and transmit the first clock signal (Adjusting and transmitting the first clock signal: Ma, Figure 6 and col.10:56-58), and
output a first target clock signal (Delay line 640 outputting a first target clock signal CKi: Ma, Figure 6 and col.10:56-58); and
a phase processing module (Multi-phase generator 620: Ma, Figure 6),
configured to receive a preset control code (Present control code VBias: Ma, Figure 1 and col.5:3-6) and the first target clock signal (First clock signal Cki: Ma, Figure 6),
perform delay processing on the first target clock signal based on the preset control code (Delay clock signal based on VBias and first clock signal: Ma, Figure 1 and col.5:6-11), and
output at least one delayed target clock signal (Output clock signals CK0, CK90, CK180, and CK270: Ma, Figure 1);
wherein the first target clock signal and the at least one delayed target clock signal constitute a set of target clock signals (Disclosing the set of clock signals: Ma, col.5:16); and
a phase difference between two adjacent clock signals in the set of target clock signals is a preset value (The clock signals having a preset phase difference: Ma, col.5:15-17).
Regarding Claim 2, Ma discloses the delay locked loop of claim 1, wherein
the preset value is 90 degrees (The preset phase difference being 90 degrees: Ma, col.5:17); and
the at least one delayed target clock signal comprises
a second target clock signal (CK90: Ma, col.5:18),
a third target clock signal (CK180: Ma, col.5:18) and
a fourth target clock signal (CK270: Ma, col.5:18).
Regarding Claim 3, Ma discloses the delay locked loop of claim 2, wherein the phase processing module comprises:
a first delay chain,
configured to receive the preset control code and the first target clock signal,
perform delay processing on the first target clock signal based on the preset control code, and
output the second target clock signal (First delay chain receiving the first clock signal DCCCLK/CK0, perform delay processing based on VBias control signal, and output second clock signal CK90: Ma, Figure 1 as annotated below);
a second delay chain,
configured to receive the preset control code and the second target clock signal,
perform delay processing on the second target clock signal based on the preset control code, and
output the third target clock signal (Second delay chain receiving the second clock signal CK90, perform delay processing based on VBias control signal, and output third clock signal CK180: Ma, Figure 1 as annotated below); and
a third delay chain,
configured to receive the preset control code and the third target clock signal,
perform delay processing on the third target clock signal based on the preset control code, and
output the fourth target clock signal (Third delay chain receiving the third clock signal CK180, perform delay processing based on VBias control signal, and output fourth clock signal CK270: Ma, Figure 1 as annotated below).
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Regarding Claim 14, Ma discloses the delay locked loop of claim 2, wherein the delay locked loop further comprises
a control module (Control module 120: Ma, Figure 1);
wherein the control module is configured to generate a delay line control signal (Control module 120, with Charge pump 140, outputting a Vctrl signal that is converted into the Vbias control signal: Ma, Figure 1); and
the first variable delay line is specifically configured to
receive the delay line control signal (First variable delay line receiving the control signal: Ma, Figure 1),
adjust and transmit the first clock signal based on the delay line control signal, and output the first target clock signal (Vbias being used to adjust the delay time of adjustable delay line 110: Ma, Figure 1 and col.3:31-34).
Regarding Claim 17, Ma discloses a clock synchronization circuit, comprising
the delay locked loop of claim 1 (Delay locked loop generator: Ma, Figure 6) and
a data selection module (Data selection clock tree 615: Ma, Figure 6), and
signal transmission paths being provided between the delay locked loop and the data selection module (Signal paths C0, C90, C180, C270, and C360 between DLL and clock tree 615: Ma, Figure 6);
wherein the delay locked loop is configured to receive the initial clock signal and output the set of target clock signals (DLL receiving clock inputs 610 and 630 and output clock signals C0, C90, C180, C270, and C360: Ma, Figure 6);
a phase difference between two adjacent clock signals in the set of target clock signals is a preset value (Output clock signals having a preset 90 degree phase difference: Ma, col.4:4-11); and
the data selection module is configured to receive the set of target clock signals via the signal transmission paths, and sample and select data signals for output by using the set of target clock signals to obtain a target data signal (The clock tree may be included in the DLL generator and provide feedback signal 655 to obtain the target data signal: Ma, col.10:63-11:5).
Regarding Claim 18, Ma discloses a memory, comprising
the clock synchronization circuit of claim 17 (Showing the clock synchronization circuit 750 in situ in a memory device: Ma, Figure 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-5 and 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,872,924 B2 to Yantao Ma (hereafter Ma) in view of US 8,253,466 B2 to Brad Porcher Jeffries, et al. (hereafter Jeffries) and US 10,305,496 B2 to Yasuhiro Sudo, et al. (hereafter Sudo).
Regarding Claim 4, Ma discloses the delay locked loop of Claim 3 but fails to disclose the further limitations of Claim 4. Jeffries, however, discloses a delay locked loop as in Claim 3, wherein
the pre-processing module is specifically configured to perform frequency division processing and phase division processing on the initial clock signal and output a first clock signal and a second clock signal (Disclosing a processor taking with input clock signal clk and outputting signals I and Q: Jeffries, Figure 1);
wherein
a clock period of the first clock signal is twice a clock period of the initial clock signal (Clock period I being twice that of clock period clk: Jeffries, Figure 1 and col.2:35-40),
a clock period of the second clock signal is the same as the clock period of the first clock signal (Clock period Q being the same as clock period I: Jeffries, Figure 1), and
a phase difference between the first clock signal and the second clock signal is 90 degrees (The clock period between Q and I being 90 degrees: Jeffries, Figure 1 and col.2:38-50);
Jeffries teaches creating a pair of output clock signals with twice the clock period of the input clock signal generates signals with an appropriate 90 degree phase difference necessary to generate a correct quadrature phase relationship (Jeffries, col.4:4-13).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the frequency processing module of Jeffries with the clock signal generator of Ma, with a reasonable expectation of success. Both inventions are known in the field of clock signal synchronization and the combination of known inventions with predictable results is obvious and not patentable.
Jeffries does not explicitly disclose the delay locked loop further comprising a time-to-digital conversion module. Sudo, however, discloses a delay locked loop circuit further comprising:
the delay locked loop further comprising a time-to-digital conversion module (Teaching a time to digital conversion circuit 20: Sudo, Figure 1 and col.6:41) ; wherein
the time-to-digital conversion module is configured to receive the first clock signal and the second clock signal (Conversion module 20 receiving two input signals: Sudo, col.6:41-44), and
output the preset control code based on the phase difference between the first clock signal and the second clock signal (Conversion module 20 outputting the phase difference between the input signals as a digital value DQ: Sudo, col.6:41-44).
Sudo teaches the time-to-digital circuit permits a subsequent synchronization circuit to synchronize the signals, as desired, without the need for additional complicated circuitry (Sudo, col. 8:47-61).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the time-to-digital circuit to the clock signal generator of Ma, with a reasonable expectation of success. Both inventions are known in the field of clock signal synchronization and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 5, Ma discloses the delay locked loop of claim 4, wherein
the preset control code comprises A-bit parameters (Disclosing preset control signals: Ma, col.3:64-65), and
the time-to-digital conversion module comprises:
an operation module, configured to
receive the first clock signal and the second clock signal (Receiving a first and second clog signal: Sudo, col.6:41-44),
perform logic operation on the first clock signal and the second clock signal (Performing a logical operation on the two clock signals: Sudo, col.6:41-45), and
output a sampling base signal and a sampling clock signal (Outputting data based on the logical operation: Sudo, col.6:41-45);
wherein the sampling base signal is used to indicate the phase difference between the first clock signal and the second clock signal (Where the output data indicates the phase difference between the input signals: Sudo, col.6:49-52);
a fourth delay chain, comprising
A first delay units connected in series (Disclosing an additional delay chain outputting signal 114E: Ma, Figure 1),
configured to receive the sampling clock signal and output A sampling indication signals (Modified by sampling indication signal VBias: Ma, Figure 1);
wherein an i-th first delay unit in the first delay units outputs an i-th sampling indication signal in the sampling indication signals (VBias generated based on sampling difference between first clock signal 114A and subsequent signal 114C: Ma, Figure 1); and
a sampling module,
configured to receive the A sampling indication signals and the sampling base signal (Phase detector 120 sampling base signal and later sampling signals 114C and 114E: Ma, Figure 1) , and
perform sampling processing on the sampling base signal by using the i-th sampling indication signal (Sample processing of signals 114A and 114C: Ma, Figure 1), and
output an i-th-bit parameter in the preset control code (Phase detector 120 outputting VCntrl, which is converted to VBias: Ma, Figure 1);
wherein i and A are natural numbers, and i is less than or equal to A (i sample 114C less than total A delay circuits: Ma, Figure 1).
Regarding Claim 9, Ma discloses the delay locked loop of claim 5, wherein
the first delay chain, the second delay chain and the third delay chain each comprises A second delay units connected in series (Delay chain, such as 110 and 160, consisting of a series of delay units: Ma, Figure 1), and
the i-th-bit parameter in the preset control code is used to control an i-th second delay unit in the second delay units to be in an open state or a closed state (Each delay circuit adjusted by Vbias: Ma, Figure 1);
the first delay chain is specifically configured to
perform delay processing on the first target clock signal by using the A second delay units of the first delay chain in the open state and output the second target clock signal (First delay chain, see modified Figure 1 for reference, processes the incoming signal, preset delay, and phase delay signal Vbias to output a next step signal: Ma, Figure 1);
the second delay chain is specifically configured to
perform delay processing on the second target clock signal by using the A second delay units of the second delay chain in the open state and output the third target clock signal (Second delay chain processes the incoming signal, preset delay, and phase delay signal Vbias to output a next step signal: Ma, Figure 1); and
the third delay chain is specifically configured to
perform delay processing on the third target clock signal by using the A second delay units of the third delay chain in the open state and output the fourth target clock signal (Third delay chain processes the incoming signal, preset delay, and phase delay signal Vbias to output a next step signal: Ma, Figure 1).
Regarding Claim 10, Ma discloses the delay locked loop of claim 5, wherein
first B-bit parameters in the preset control code are a first value, and last (A-B)-bit parameters of the preset control code are a second value;
wherein B is a positive integer less than or equal to A (First output clock signal CK0 is unmodified by delay, therefore preset control is zero and less than A: Ma, Figure 1);
the first delay chain, the second delay chain and the third delay chain each comprises A second delay units connected in series, and
the preset control code indicates that an output signal of a B-th second delay unit in the second delay units is used as an output signal of a delay chain (Output of the first clock signal is used as input of next delay circuit and as input to phase controller, leading to Vbias phase control signal: Ma, Figure 1);
the first delay chain is specifically configured to
receive the first target clock signal through a first one in the A second delay units of the first delay chain and determine an output signal of a B-th second delay unit in the second delay units as the second target clock signal (Output of the first clock signal is used as input of next delay circuit and as input to phase controller, leading to Vbias phase control signal; next delay circuit incorporates input signal, phase control signal, and preset delay to generate output signal: Ma, Figure 1);
the second delay chain is specifically configured to
receive the second target clock signal through a first one in the A second delay units of the second delay chain and determine an output signal of a B-th second delay unit in the second delay units as the third target clock signal (Output of the first clock signal is used as input of next delay circuit and as input to phase controller, leading to Vbias phase control signal; next delay circuit incorporates input signal, phase control signal, and preset delay to generate output signal: Ma, Figure 1); and
the third delay chain is specifically configured to
receive the third target clock signal through a first one in the A second delay units of the third delay chain and determine an output signal of a B-th second delay unit in the second delay units as the fourth target clock signal (Output of the first clock signal is used as input of next delay circuit and as input to phase controller, leading to Vbias phase control signal; next delay circuit incorporates input signal, phase control signal, and preset delay to generate output signal: Ma, Figure 1).
Regarding Claim 11, Ma discloses the delay locked loop of claim 9, wherein
each of the A second delay units connected in series has a same structure as a respective one of the A first delay units connected in series (Each of the delay circuits in the series is the same as the other delay circuits: Ma, Figure 4).
Regarding Claim 12, Ma discloses the delay locked loop of claim 10, wherein
each of the A second delay units connected in series has a same structure as a respective one of the A first delay units connected in series (Each of the delay circuits in the series is the same as the other delay circuits: Ma, Figure 4).
Regarding Claim 13, Jeffries discloses the delay locked loop of claim 4, wherein the pre-processing module comprises:
a receiving module (Disclosing clock converter 86: Jeffries, Figure 5 and col.5:25),
configured to receive the initial clock signal and output a clock signal to be processed (Clock converter 86 outputting a clock differential clock signal: Jeffries, Figure 5 and col.5:25);
wherein a clock period of the clock signal to be processed is the same as the clock period of the initial clock signal (The output differential clock signal having the same period as the initial clock signal: Jeffries, col.5:25); and
a conversion module,
configured to receive the clock signal to be processed (A conversion module 80 configured to receive the clock signal: Jeffries, Figure 5),
perform frequency division and phase division processing on the clock signal to be processed, and output the first clock signal and the second clock signal (Conversion module 80 configured to perform the frequency and phase division and output two clock signals: Jeffries, Figure 5).
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,872,924 B2 to Yantao Ma (hereafter Ma), US 8,253,466 B2 to Brad Porcher Jeffries, et al. (hereafter Jeffries) and US 10,305,496 B2 to Yasuhiro Sudo, et al. (hereafter Sudo), in view of US 6,765,976 B1 to Jong-Hoon Oh (hereafter Oh).
Regarding Claim 6, Ma discloses the delay locked loop of Claim 5, but fails to disclose the further limitations of Claim 6. Oh, however, discloses a delay locked loop as in Claim 5, wherein
the operation module comprises a first flip-flop, a second flip-flop, an AND gate, and a buffer;
wherein
an input end of the first flip-flop receives a power supply signal, a clock end of the first flip-flop receives the second clock signal, an input end of the second flip-flop receives the power supply signal, and a clock end of the second flip-flop receives the first clock signal (Compare circuits 350 and 354 taking input of initial clock signal C_IN1 and delayed OUT_CLK1, with supply and ground signals: Oh, Figure 5);
a first input end of the AND gate is connected with a negative output end of the first flip-flop, a second input end of the AND gate is connected with a positive output end of the second flip-flop (Logic gate connected with output of compare circuits 350 and 354: Oh, Figure 5), and
an output end of the AND gate is used to output the sampling base signal (Output of the logic gate outputs sampling base signals SL and SR: Oh, Figure 5); and
an input end of the buffer is connected with a positive output end of the second flip-flop (Buffer circuit 418 connected to output of delay circuit: Oh, Figure 6), and
an output end of the buffer is used to output the sampling clock signal (Modified clock signal CM output from buffer circuit: Oh, Figure 6).
Oh teaches this circuit arrangement allows for control of multiple periodic signals with minimal circuitry (Oh, col.6:33-44).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the delay circuit of Oh with the clock signal generator of Ma with a reasonable expectation of succuss. Both inventions are well known in the field of phase locked clock signal management and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 7, Ma discloses the delay locked loop of Claim 5, but fails to disclose the further limitations of Claim 7. Oh, however, discloses a delay locked loop as in Claim 5, wherein
the sampling module comprises A third flip-flops (The DLL consisting of a series of additional delay circuits: Oh, Figure 9);
wherein an input end of an i-th third flip-flop in the third flip-flops receives the sampling base signal, a clock end of the i-th third flip-flop receives the i-th sampling indication signal (Delay circuits taking inputs of base signal and sampling control: Oh, Figure 9), and
a positive output end of the i-th third flip-flop outputs the i-th-bit parameter in the preset control code (Output of each delay circuit outputs delayed signal: Oh, Figure 9).
Oh teaches this circuit arrangement allows for control of multiple periodic signals with minimal circuitry (Oh, col.6:33-44).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the delay circuit of Oh with the clock signal generator of Ma with a reasonable expectation of succuss. Both inventions are well known in the field of phase locked clock signal management and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 8, Ma discloses the delay locked loop of claim 7, wherein the time-to-digital conversion module is further configured to
send the preset control code to the phase processing module after
the A third flip-flops complete sampling processing and the delay locked loop completes phase locking processing (Each subsequent delay module outputting a signal to phase processing: Ma, Figure 1).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,872,924 B2 to Yantao Ma (hereafter Ma) in view of US 7,042,971 B1 to Ian M. Flanagan, et al. (hereafter Flanagan).
Regarding Claim 15, Ma discloses the delay locked loop of claim 14, wherein
the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are used for data sampling processing after each passing through a respective signal transmission path (First through fourth clock signals used for data sampling: Ma, Figure 1);
wherein the control module comprises:
a feedback module,
configured to receive the first clock signal and output an simulation clock signal (Feedback module receiving primary clock signal Fref and outputting a simulated waveform: Flanagan, Figure 1),
the simulation clock signal being used to simulate a waveform of the first target clock signal after passing through the signal transmission path (Auxiliary Delay Line 48 used to generate a secondary clock signal for phase lock testing: Flanagan, Figure 1);
a detection module,
configured to receive the first clock signal and the simulation clock signal (Lock detection circuit 56 receiving first clock signal Fref and Aux Delay Line output Ffb: Flanagan, Figure 1),
perform phase detection on the first clock signal and the simulation clock signal (Determining lock detection: Flanagan, Figure 1), and
obtain a phase detection signal (Producing a phase lock detection signal, Vlock: Flanagan, Figure 1); and
a parameter adjusting module,
configured to receive the phase detection signal (Output latch receiving the phase detection signal: Flanagan, Figure 1), and
output the delay line control signal based on the phase detection signal (Outputting a signal based on the phase detection signal: Flanagan, Figure 1).
Flanagan teaches the auxiliary delay line module permits the delay-locked loop circuit to perform a self-text operation and verify the DLL is operating within predefined specifications (Flanagan, col.2:59-67).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the delay-locked loop self-test module of Flanagan with the clock signal generator of Ma with a reasonable expectation of success. Both inventions are known in the field of quadrature clock signal generators and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 16, Flanagan discloses the delay locked loop of claim 15, wherein the feedback module comprises:
a second variable delay line, configured to
receive the first clock signal and the delay line control signal (Variable delay line receiving the first clock signal and delay line control signal: Flanagan, Figure 1),
adjust and transmit the first clock signal based on the delay line control signal (Flanagan, Figure 1), and
output a replica clock signal (Outputting a replica clock signal: Flanagan, Figure 1);
wherein
a structure of the second variable delay line is the same as a structure of the first variable delay line (The structure of the variable delay line the same as base variable delay line: Flanagan, Figure 1), and
the replica clock signal is used to simulate the waveform of the first target clock signal (The replica delay module simulating delay of transmission signal: Flanagan, Figure 1); and
a replica delay module,
configured to receive the replica clock signal (Delay module receiving the replica clock signal Fout: Flanagan, Figure 1),
perform delay processing on the replica clock signal (Delaying the replica clock signal Fout: Flanagan, Figure 1), and
output the simulation clock signal (Outputting simulation clock signal Ffb: Flanagan, Figure 1);
wherein
the replica delay module is configured to simulate a delay of the signal transmission path (The replica delay module simulating delay of transmission signal: Flanagan, Figure 1).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,872,924 B2 to Yantao Ma (hereafter Ma) in view of US 2021/0375341 A1 to Yunyun Xiao, et al. (hereafter Xiao).
Regarding Claim 19, Ma discloses the memory of claim 18 but fails to disclose the further limitations of Claim 19. Xiao, however, discloses a memory, wherein
the memory conforms to a DDR5 specification (Memory conforming to DDR5 specification: Xiao, ¶[0026]).
Xiao teaches DDR5 ready memory permits the memory to take advantage of different lengths of commands consisting of one or more clock cycles (Xiao, ¶[0004]).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the clock signal generator of Ma with the DDR5 ready memory of Xiao, with a reasonable expectation of success. Both devices are well known in modern memory controls and the combination of known inventions with a reasonable expectation of success are obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2003/0169084 A1 to Tyler J. Gomm, et al.: Teaching a clock delay circuit with phase delay and model delay circuit for phase verification.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/JEROME LEBOEUF/ Primary Examiner, Art Unit 2824 – 08/21/2025