DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (2021/0035990).
Re claim 1, Lee et al. disclose (Fig. 6A) a semiconductor substrate (201); a plurality of conductive lines (310a/310b/310c/310d/310e/310f/310g/310h) extending on the semiconductor substrate in a horizontal direction and overlapping each other in a vertical direction; a plurality of insulating layers (210a/210b/210c/210d/210e/210f/210g/210h) between pairs of conductive lines of the plurality of conductive lines and extending in the horizontal direction; and a channel structure (410/420) passing through the plurality of conductive lines and the plurality of insulating layers, wherein the channel structure includes: a core insulating layer (450), a channel layer (430) on a side wall and a bottom surface of the core insulating layer, a gate insulating layer (420) on an outer wall of the channel layer, and a ferroelectric layer (410) on an outer wall of the gate insulating layer (Fig. 6A).
Claim(s) 11, 17 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Harari (2023/0262988).
Re claim 11, Harari discloses (Fig. 1) a semiconductor substrate (12); a plurality of conductive lines (16) extending on the semiconductor substrate in a horizontal direction and overlapping each other in a vertical direction; a plurality of insulating layers (15) between pairs of conductive lines of the plurality of conductive lines and extending in the horizontal direction; and a channel structure (26) passing through the plurality of conductive lines and the plurality of insulating layers (Fig. 1a), wherein the channel structure includes: a core insulating layer (44), a channel layer (26) on a side wall and a bottom surface of the core insulating layer, a gate insulating layer (27) on an outer wall of the channel layer, and a high-k pattern (25) and a ferroelectric pattern (27) alternating in the vertical direction on an outer wall of the gate insulating layer (Fig. 1a~ [0049]).
Re claim 17, Harari discloses wherein: each conductive line of the plurality of conductive lines faces the ferroelectric pattern (27), and each insulating layer of the plurality of insulating layers faces the high-k pattern (25) (Fig. 1a).
Re claim 18, Harari discloses (Fig. 3) a main substrate (160); an integrated circuit device on the main substrate ([0070]); and a controller (166) electrically connected to the integrated circuit device on the main substrate ([0071]), wherein:
a semiconductor substrate (12); a plurality of conductive lines (16) extending on the semiconductor substrate in a horizontal direction and overlapping each other in a vertical direction; a plurality of insulating layers (15) between pairs of conductive lines of the plurality of conductive lines and extending in the horizontal direction; and a channel structure (26) passing through the plurality of conductive lines and the plurality of insulating layers (Fig. 1a), wherein the channel structure includes: a core insulating layer (44), a channel layer (26) on a side wall and a bottom surface of the core insulating layer, a gate insulating layer (27) on an outer wall of the channel layer, and a high-k pattern (25) and a ferroelectric pattern (27) alternating in the vertical direction on an outer wall of the gate insulating layer (Fig. 1a~ [0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Harari as applied to claims 11, 17 and 19 above, and further in view of the following comments.
Re claim 18, Harari does not specifically disclose wherein a length of each insulating layer of the plurality of insulating layers in the vertical direction is greater than or equal to a length of the facing high-k pattern in the vertical direction.
One of ordinary skill in the art would have been led to the recited length through routine experimentation to achieve a desired device dimension, device associated characteristics and device density on the finished wafer.
In addition, the selection of length, it's obvious because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996)(claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Note that the specification contains no disclosure of either the critical nature of the claimed length or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen length or upon another variable recited in a claim, the Applicant must show that the chosen length is critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Re claim 20, Harari discloses wherein: the main substrate (160) further includes wiring patterns (156/158) electrically connecting the integrated circuit device (155) to the controller (166), the integrated circuit device further includes an insulating liner conformally surrounding an upper surface, a lower surface, and a side surface of each of the plurality of conductive lines ([0071]), and the insulating liner is in contact with the ferroelectric layer of the channel structure ([0068]).
Harari does not disclose wherein the liner includes a metal oxide layer.
The use of a metal oxide material as a liner was well known in the art before the effective filing date of the invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the known material because it works as a barrier to prevent corrosion and diffusion of other materials.
Allowable Subject Matter
Claims 2-10 and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pending the correction of issues outlined in the rejection above, the following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest the following in combination the remaining limitations called for in each claim:
further comprising an insulating liner conformally surrounding an upper surface, a lower surface, and a side surface of each of the plurality of conductive lines, wherein the insulating liner includes a metal oxide layer and is in contact with the ferroelectric layer of the channel structure, as recited in claim 2;
wherein: the ferroelectric layer includes hafnium zirconium oxide (HfZrO), and a ratio of hafnium (Hf) to zirconium (Zr) in the HfZrO is about 1:1, as recited in claim 3;
wherein a thickness of the ferroelectric layer in the horizontal direction is about 30A to about 100 A, as recited in claim 4;
wherein: the metal oxide layer is between each of the plurality of conductive lines and the ferroelectric layer, and the metal oxide layer includes aluminum oxide (Al203), as recited in claim 5;
wherein the gate insulating layer includes a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer sequentially on the outer wall of the channel layer, as recited in claim 6;
wherein movement of electrons or holes stored in the charge storage layer is suppressed by remanent polarization of the ferroelectric layer, as recited in claim 7;
wherein the ferroelectric layer is between the metal oxide layer and the blocking dielectric layer, as recited in claim 8;
wherein: the tunneling dielectric layer includes silicon oxide (SiO), the charge storage layer includes silicon nitride (SiN), and the blocking dielectric layer includes SiO, as recited in claim 9;
wherein a thickness of the SiO included in the blocking dielectric layer is about 20 A to about 50 A, as recited in claim 10;
further comprising an insulating liner conformally surrounding an upper surface, a lower surface, and a side surface of each of the plurality of conductive lines, wherein the insulating liner includes a metal oxide layer and is in contact with the ferroelectric pattern of the channel structure., as recited in claim 12;
wherein: the metal oxide layer includes aluminum oxide (A1203), the high-k pattern includes hafnium oxide (HfO), and the ferroelectric pattern includes hafnium aluminum oxide (HfAlO), as recited in claim 13;
wherein aluminum (Al) included in the ferroelectric pattern spreads in a process of crystallizing the metal oxide layer, and HfAlO exists in a form of nanocrystals, as recited in claim 14;
wherein the process of crystallizing the metal oxide layer is performed by a spike annealing process, as recited in claim 15;
wherein an amount of Al in HfAlO included in the nanocrystals is about 4.5 %, as recited in claim 16.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2024/0029789 A1, US 12,520,497 B2 and US 12,588,251 disclose a similar configuration for a memory device with a ferroelectric layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE MANDALA whose telephone number is (571)272-1858. The examiner can normally be reached 8:00-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHELLE MANDALA/Primary Examiner, Art Unit 2893 March 26, 2026
Prosecution Insights