DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 6, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Anderson et al. (US 2024/0339452).
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Anderson teaches (FIG. 17):
A microelectronic structure comprising:
a stack nanosheet transistor comprising a lower nanosheet transistor (lower 108s) and an upper nanosheet transistor (upper 108s), wherein the lower nanosheet transistor includes a lower source/drain (142), wherein the upper nanosheet transistor includes an upper source/drain (146);
an airgap (152) located between the upper source/drain and the lower source/drain, wherein the airgap is vertically aligned with the upper source/drain and the lower source/drain; and
a first layer (156) located between the airgap and the lower source/drain.
Regarding claim 2, Anderson teaches (FIG. 17):
The microelectronic structure of claim 1, wherein the first layer includes a horizontal section and at least two vertical sections.
Regarding claim 3, Anderson teaches:
The microelectronic structure of claim 2, wherein the first layer has a U-shaped profile as view from a cross section that is perpendicular to a gate direction (FIG. 17).
Regarding claim 4, Anderson teaches:
The microelectronic structure of claim 3, wherein the first layer is comprised of SiN ([0081]).
Regarding claim 5, Anderson teaches:
The microelectronic structure of claim 1, wherein the lower nanosheet transistor has a width larger than a width of the upper nanosheet transistor as measured in parallel to the gate direction ([0028]).
Regarding claim 6, Anderson teaches (FIG. 17):
The microelectronic structure of claim 5, further comprising: a lower source/drain contact (168) that extends through the first layer to make contact with the lower source/drain.
Regarding claim 18, Anderson teaches (FIG. 17):
A method comprising:
forming a stack nanosheet transistor comprising a lower nanosheet transistor (lower 108s) and an upper nanosheet transistor (upper 108s), wherein the lower nanosheet transistor includes a lower source/drain (142), wherein the upper nanosheet transistor includes an upper source/drain (146);
forming an airgap (152) located between the upper source/drain and the lower source/drain, wherein the airgap is vertically aligned with the upper source/drain and the lower source/drain (FIG. 17); and
forming a first layer (156) located between the airgap and the lower source/drain (FIG. 17).
Allowable Subject Matter
Claims 7 – 17 are allowed.
Claims 19 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to teach or fairly render obvious a second layer located directly on top of the first layer, wherein the second layer is located between the airgap and the lower source/drain, in combination with the other limitations of the claims.
Khaderbad et al. (US 2023/0068065) teaches a multiple layer isolation between upper and lower source/drain structures, but there is no teaching or motivation to modify one of the layers to be an air gap.
Xie et al. (US 2021/0296184) teaches an airgap between upper and lower source/drain structures, but there are no additional layers on the airgap surface.
Xie et al. (US 11,069,684) teaches an airgap between upper and lower source/drain structures, but there are no additional layers on the airgap surface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624