Prosecution Insights
Last updated: April 19, 2026
Application No. 18/529,008

METHODS FOR FORMING THIN FILM RESISTOR

Non-Final OA §102
Filed
Dec 05, 2023
Examiner
HARRISON, MONICA D
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
94%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
857 granted / 936 resolved
+23.6% vs TC avg
Minimal +3% lift
Without
With
+2.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
17 currently pending
Career history
953
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
37.5%
-2.5% vs TC avg
§102
44.2%
+4.2% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 936 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wakisaka (US 2005/0218473). Regarding claim 15, Wakisaka discloses a resistor structure (Figure 3), comprising: a resistor sheet (Figure 3, reference 3); and two landing pads (Figure 3, reference 4) at opposite ends of the resistor sheet (Figure 3, reference 3) with sidewall spacers (Figure 3, reference 5) around each landing pad (Figure 3, reference 4). Regarding claim 16, Wakisaka discloses wherein peripheral portions of the sidewall spacers (Figure 3, reference 5) extend below the resistor sheet (Figure 3, reference 3). Regarding claim 17, Wakisaka discloses wherein each landing pad (Figure 3, reference 4) comprises a barrier metal layer (Figure 3, reference 9) and a hard mask layer (Figure 3, reference 10). Regarding claim 18, Wakisaka discloses further comprising a buffer layer (Figure 3, reference 1) below the resistor sheet (Figure 3, reference 3) and a capping layer (Figure 3, reference 7) covering the resistor sheet (Figure 3, reference 3) and the two landing pads (Figure 3, reference 4). Allowable Subject Matter Claims 1-14 and 19-20 are allowed over the prior art of record. Reasons for Allowance The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest a method for forming a resistor structure, comprising: etching the spacer film layer to form sidewall spacers around the two landing pads; and etching away the exposed portion of the barrier metal layer between the two landing pads to form the resistor structure (claim 1) and a method for forming a resistor structure in a back-end-of-line process, comprising: etching to form a resistor stack from the resistor material layer, the barrier metal layer, and the hard mask layer; etching the hard mask layer to expose a portion of the barrier metal layer between two ends of the resistor stack; partially etching the exposed portion of the barrier metal layer to form two landing pads at the ends of the resistor stack ;applying a spacer film layer over the resistor stack; etching the spacer film layer to form sidewall spacers around the two landing pads; completely etching away the exposed portion of the barrier metal layer between the two landing pads to form the resistor structure; applying a capping layer over the resistor structure; forming a second dielectric layer upon the substrate and over the resistor structure; etching to form vias to the two landing pads; filling the vias with an electrically conductive material; and forming metal contacts over the vias (claim 19) as described in these independent claims and in the context of their recited processes, along with their depending claims. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kuo et al (US 2022/0149147 A1) discloses a resistor structure (Figure 12A, reference 302a), a resistor sheet (Figure 12A, reference 144), two landing pads (Figure 12A, reference 120) at opposite ends of the resistor sheet (Figure 12A, reference 114), and an exposed portion of a barrier metal layer (Figure 12A, reference 118) between the two landing pads (Figure 12A, reference 120). However, Kuo et al does not disclose the above allowable claimed subject matter. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MONICA D HARRISON/Primary Examiner, Art Unit 2815 mdh February 3, 2026
Read full office action

Prosecution Timeline

Dec 05, 2023
Application Filed
Feb 03, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
94%
With Interview (+2.6%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 936 resolved cases by this examiner. Grant probability derived from career allow rate.

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