DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-15) in the reply filed on 7/27/2026 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/26/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jo et al (US Publication No. 2023/0352529).
Regarding claim 1, Jo discloses an integrated circuit (IC) comprising: a top device Fig 1A-1B, 10U; and a bottom device Fig 1A-1B, 10L positioned under the top device Fig 1A-1B, 10U; wherein the top device comprises a first nanosheet and a second nanosheet Fig 2, 120; wherein the bottom device comprises a third nanosheet and a fourth nanosheet Fig 2, 110; and wherein a space Fig 3, INT2 between the first nanosheet and the second nanosheet is greater than a space Fig 3, INT1 between the third nanosheet and the fourth nanosheet ¶0036.
Regarding claim 2, Jo discloses a stacked device configuration comprising: the top device; the bottom device; and an isolation region Fig 2, 130 operable to electrically isolate the bottom device from the top device ¶0033; a top gate around exposed surfaces of the first nanosheet and the second nanosheet; and a bottom gate around exposed surface of the third nanosheet and the fourth nanosheet Fig 1A-1B, 130.
Regarding claim 3, Jo discloses wherein a width dimension of the top gate is different from a width dimension of the bottom gate Fig 1A-1D.
Regarding claim 4, Jo discloses wherein a work function of the top gate is different from a work function of the bottom gate ¶0051-0052.
Regarding claim 5, Jo discloses top source or drain (S/D) regions electronically coupled to the first nanosheet; and bottom S/D regions electronically coupled to the third nanosheet; wherein a doping type of the top S/D regions is different from a doping type of the bottom S/D regions ¶0034, 0038, 0051.
Regarding claim 6, Jo discloses an integrated circuit (IC) comprising: a top channel Fig 2, 120 associated with a first device Fig 1A-1B, 10U and comprising a first nanosheet stack; wherein the first nanosheet stack comprises a first nanosheet and a second nanosheet Fig 2, 120; and a bottom channel Fig 2, 110 positioned below the top channel Fig 2, 120, associated with a second device Fig 1A-1B, 10L, and comprising a second nanosheet stack Fig 2, 110; wherein the second nanosheet stack comprises a third nanosheet and a fourth nanosheet Fig 2, 110; and wherein a space Fig 3, INT2 between the first nanosheet and the second nanosheet is greater than a space Fig 3, INT1 between the third nanosheet and the fourth nanosheet Fig 1A-3.
Regarding claim 7, Jo discloses a top gate around exposed surfaces of the first nanosheet and the second nanosheet Fig 1A-1E, Fig 7.
Regarding claim 8, Jo discloses a bottom gate around exposed surface of the third nanosheet and the fourth nanosheet Fig 1A-1E, Fig 7.
Regarding claim 9, Jo discloses wherein a width dimension of the top gate is different from a width dimension of the bottom gate Fig 1A-1E, Fig 7.
Regarding claim 10, Jo discloses a work function of the top gate is different from a work function of the bottom gate¶0051-0052.
Regarding claim 11, Jo discloses a width dimension of the top gate is different from a width dimension of the bottom gate; and a work function of the top gate is different from a work function of the bottom gate¶0051-0052 Fig 1A-1E, Fig 7.
Regarding claim 12, Jo discloses top source or drain (S/D) regions electronically coupled to the top channel; and bottom S/D regions electronically coupled to the bottom channel ¶0034, 0038, 0051.
Regarding claim 13, Jo discloses wherein a doping type of the top S/D regions is different from a doping type of the bottom S/D regions ¶0034, 0038, 0051.
Regarding claim 14, Jo discloses wherein: the first device comprises an n-type transistor; and the second device comprises a p-type transistor ¶0034, 0038, 0051.
Regarding claim 15, Jo discloses wherein: the first device comprises a p-type transistor; and the second device comprises an n-type transistor ¶0034, 0038, 0051.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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