DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 in the reply filed on 5/18/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6-7 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chang et al (US 2014/0065802).
1. A semiconductor device, comprising:
a substrate (Fig.1 (104) and [0027]);
first and second field effect transistors (FETs) of opposite polarity (Fig.8-11 (802a-c/402a-c) and [0037-0040; see also CMOS 0002]), the first FET (Fig.8-11 (802a/402a) and [0037-0040]) being disposed on a first side of the substrate (left side) and comprising first work function metal (WFM) (Fig.8 (802a) and [0037]) and the second FET (Fig.8-11 (802c/402c) and [0037-0040]) being disposed on a second side of the substrate (right side) and comprising second WFM (Fig.8 (802c) and [0037]);
a first gate dielectric (Fig.6 (602c) and [0033]) disposed over at least the first side of the substrate (right side); and
a second gate dielectric (Fig.6 (602c) and [0033]) disconnected from the first gate dielectric (Fig.6 (602a) and [0033]) and disposed over at least the second side of the substrate (right side), the second WFM (Fig.9 (802c) and [0037]) being aligned with the second gate dielectric (Fig.9 (602c) and [0033]) and the first WFM (Fig.9 (802a) and [0039]) extending beyond the first gate dielectric (Fig.6 (602a) and [0033]).
2. The semiconductor device according to claim 1, wherein the first WFM contacts (Fig.8 (802b) and [0039]) the second WFM (Fig.8 (802b) and [0039]) in a plane aligned with an edge of the second gate dielectric (Fig.8 (602b) and [0033]).
4. The semiconductor device according to claim 1, wherein the first and second FETs are finFETs (Abstract).
6. The semiconductor device according to claim 1, wherein the first and second gate dielectrics are different materials [0033].
7. The semiconductor device according to claim 1, wherein the first gate dielectric comprises one of an interfacial layer and a high-k dielectric and the second gate dielectric comprises an interfacial layer and a high-k dielectric [0033].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 2014/0065802).
Chang teaches to manipulate the threshold voltage of FinFETs using different work function materials, however fails to explicitly teach applying this to nanosheet and VTFETs as recited in claims 3 and 5:
3. The semiconductor device according to claim 1, wherein the first and second FETs are nanosheet transistors.
5. The semiconductor device according to claim 1, wherein the first and second FETs are vertical tunnel FETs.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang’s teachings to include utilizing work function materials to manipulate the threshold voltage characteristics of the gates for nanosheet transistors and VTFETs because both include gate structures which could be doped to obtain the desired threshold voltages and such transistor structures are well known and conventional.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xie et al (US 20210327759); and Bao et al (US 20210082915 A1; US 20220005807 A1; US 20230094258) teach similar WFMs for CMOS transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
6/27/26
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