DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (20240413213) in view of Yu et al. (20220037193)
Regarding Claim 1, in Figs. 3A-5, Park et al. discloses a microelectronic structure comprising: a first nanosheet transistor 155/112/110 that includes a first source/drain 135B/145; a second nanosheet transistor 155/112/110 that includes a second source/drain 135B/145, wherein the first source/drain and the second source/drain are aligned along a common axis, wherein the common axis is parallel to a gate 155 direction, wherein a backside width of the first source/drain 135B/145 and a backside width of the second source/drain 135B/145 are different (for example one can take 136B as the first source/drain and 145 as the second source/drain and since the top surface of source/drain region 145 is shaped and different than top surface S11 of source/drain 135B and hence the top surface S11 width of 135B is less than top surface width of shaped top surface of 145) as measured along the common axis; a bottom dielectric isolation layer 106/131 located on a backside surface of the second source/drain 135B; and a backside contact 133 is located on a backside surface of the first source/drain 145. Park et al. fails to disclose the newly added claim limitation of
a bottom dielectric isolation layer located on and in direct contact with a backside surface of the second source/drain. However, Yu et al. discloses a semiconductor device where in Figs. 12A-12E, 24A-24C, 25A-25C, 26A-26C and in paragraphs 0044, 0080, 0081, 0083 and 0084 elements 125/92 the required direct contact configuration is disclosed
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required added direct contact limitation in Park et al. as taught by Yu et al. in order to protect the epitaxial source/drain regions.
Regarding Claim 2, in Park et al, a backside interlayer dielectric layer 106 located on a backside surface of the bottom dielectric (isolation) layer 131
Regarding Claim 3, in Park et al, a shallow trench isolation liner 108 located along a sidewall of the backside interlayer dielectric layer 106; and a sacrificial plug 155 located along the sidewall of the backside interlayer dielectric layer 106.
Regarding Claim 4, in Park et al, the shallow trench isolation liner 106 and the sacrificial plug 155 are vertically aligned along the sidewall of the backside interlayer dielectric layer 106.
Regarding Claim 5, in Park et al, a frontside interlayer dielectric layer 141 located around the first source/drain and the second source/drain 145/135B.
Regarding Claim 6, in Park et al, the sacrificial plug 155 is located adjacent to the frontside interlayer dielectric layer 141.
Regarding Claim 7, in Park et al, a shallow trench isolation fill layer 131 located adjacent to and in direct contact with a sidewall of the backside contact 133.
Regarding Claim 8, t in Park et al, he sacrificial plug 155 and the shallow trench isolation liner 106 are located between the shallow trench isolation fill layer 131 and the backside interlayer dielectric layer 106.
Regarding Claim 9, in Park et al, the backside width of the first source/drain 145/135B is greater than the backside width of the second source/drain 145/135B as measured along the common axis (see the top pattern portion of 145).
Claims 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (20240413213) in view of Yun et al. (20240290689)
Regarding Claim 10, in Figs. 3A-5, Park et al. discloses a microelectronic structure comprising: a first nanosheet transistor 122/155 that includes a first source/drain 145/135B; a second nanosheet transistor 122/155 that includes a second source/drain 145/135B, wherein the first source/drain and the second source/drain are aligned along a common axis, wherein the common axis is parallel to a gate 122 direction; a placeholder PL located on a backside surface of the second source/drain 145/135B (see Fig. 3A), wherein the placeholder includes a shaft section (bottom/tapered section) and a head section (top/straight section), wherein the head section is wider (since it is not tapered) than the shaft section as measured along the common axis; and a backside contact 133 located on a backside surface of the first source/drain 145/135B. Park et al fails to disclose the newly added claim limitation,
wherein the head section is wider than the shaft section as measured along the common axis, wherein an interface width between the head section and the shaft section is less than a width of the head section. (Please note that this limitation has “an interface width”. One can take an portion of the head section or shaft section to arrive at “an interface width”). However, Yun et al. discloses a semiconductor device where in Fig. 4G and paragraph 0065 the required limitation with respect to the placeholder is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required placeholder limitation in Park et al. as taught by Yun et al. in order to increase the surface area of the backside contact.
Regarding Claim 11, in Park et al, a backside interlayer dielectric layer 106 located on a backside surface of the shaft section of the placeholder PL (see Fig. 3A).
Regarding Claim 12, in Park et al, a shallow trench isolation liner 108 located along a sidewall of the backside interlayer dielectric layer 106 and located along a sidewall of the shaft section of the placeholder PL (see Fig. 3A).
Regarding Claim 13, in Park et al, the shallow trench isolation liner 108 is in direct contact with a backside surface of the head section of the placeholder PL (see Fig. 3A).
Regarding Claim 14, in Park et al, a shallow trench isolation fill layer 131 located adjacent to and in direct contact with a sidewall of the backside contact 133 (see Fig. 4).
Regarding Claim 15, in Park et al, the shallow trench isolation liner 108 is located between the shaft section of the placeholder PL and the shallow trench isolation fill layer 131 (see Fig. 3A).
Regarding Claim 16, in Park et al, a sidewall of the head section of the placeholder PL is in contact with the shallow trench isolation fill layer 131 (see Fig. 3A).
Regarding Claim 17, in Park et al, the head section and the shaft section of the placeholder PL gives the placeholder a bolt shaped profile as viewed along the common axis.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 10/9/2026
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