CTNF 18/529,087 CTNF 85789 DETAILED ACTION Claim Objections 07-05-06 Claim 17 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 16. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-4, 8, 11, 14 and 18 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kimura US 2008/0291352 A1 (Kimura ‘352) . Regarding claims 1-4, 8, 11 and 14, Kimura discloses: An electronic device (Fig. 7), comprising: a first field-effect transistor (FET) (32 PMOSFET) comprising a first gate, a first terminal, and a second terminal; a second FET (33 NMOSFET) comprising a second gate, a third terminal, and a fourth terminal, the third terminal coupled in series to the second terminal; a first varactor circuit (C2; para 0087, “capacitance generated between a gate and a source and/or a drain of one or a plurality of MOSFETs”) comprising a first anode and a first cathode, the first cathode coupled to the first gate; a second varactor circuit (C3; para 0087, “capacitance generated between a gate and a source and/or a drain of one or a plurality of MOSFETs”) comprising a second anode and a second cathode, the second cathode coupled to the second gate; an input node (“IN”) comprising the first anode coupled to the second anode; and an output node (“OUT”) coupled to at least one of the second terminal and the third terminal. (claims 2-4, 8 and 11) Fig. 7; see CMOS inverter configuration of 32 and 33. (claim 14) Fig. 7; see inset depicting 32 showing multiple varactors. (claim 18) paras 0166-0168 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 5-7, 12, 13 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura US 2008/0291352 A1 (Kimura ‘352) . Regarding claims 5-7 and 15, Kimura ‘352 discloses: (claims 5 and 15) wherein: the first FET further comprises a first channel and a first insulator between the first gate and the first channel (considered inherent based on Kimura’s 32 PMOSFET); and the second FET further comprises a second channel and a second insulator between the second gate and the second channel (considered inherent based on Kimura’s 33 NMOSFET); (claim 6) wherein: the first varactor circuit comprises a third gate between the first anode and the first cathode, and a third insulator between the third gate and the first cathode (considered inherent based on Kimura’s C2; para 0087); and the second varactor circuit comprises a fourth gate between the second anode and the second cathode, and a fourth insulator between the fourth gate and the second cathode (considered inherent based on Kimura’s C3; para 0087); and (claim 7) wherein: the first FET further comprises a first gate oxide between the first gate and the first channel; and the second FET further comprises a second gate oxide between the second gate and the second channel (considered inherent based on Kimura’s 32 PMOSFET and 33 NMOSFET). Although Kimura ‘352 does not specifically disclose “the first insulator having a first thickness in a first direction from the first gate to the first channel equal to or less than two (2) nanometers (nm); the second insulator having a second thickness in a second direction from the second gate to the second channel equal to or less than two (2) nm; the third insulator having a third thickness equal to the first thickness in a third direction from the third gate to the first cathode; and the fourth insulator having a fourth thickness equal to the second thickness in a fourth direction from the fourth gate, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed ranges and values for the first, second, third and fourth insulator thicknesses of Kimura’s similar features (1) since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; and (2) since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272,205USPQ 215 (CCPA 1980). Regarding claims 12 and 13, as in the rejection of claim 1 above, although Kimura does not specifically disclose “a third FET comprising a third gate, a fifth terminal, and a sixth terminal, the third FET having a third breakdown voltage between the third gate and the fifth terminal; and a third varactor circuit comprising a third anode and a third cathode, the third cathode coupled to the third gate”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed third FET, third varactor and the associated connectivity within the device of Kimura since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis paper Co. v. Bemis Co., 193 USPQ 8. Regarding claims 16 and 17, Kimura discloses: wherein: the first varactor circuit comprises a third gate between the first anode and the first cathode, and a third insulator between the third gate and the first cathode (considered inherent based on Kimura’s C2; para 0087); and the second varactor circuit comprises a fourth gate between the second anode and the second cathode, and a fourth insulator between the fourth gate and the second cathode (considered inherent based on Kimura’s C3; para 0087) Although Kimura ‘352 does not specifically disclose “the third varactor comprises a fifth gate between the first anode and the third cathode, and a fifth insulator between the fifth gate and the third cathode; and the fourth varactor comprises a sixth gate between the second anode and the fourth cathode, and a sixth insulator between the sixth gate and the fourth cathode”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed third FET, third varactor and the associated connectivity within the device of Kimura since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis paper Co. v. Bemis Co., 193 USPQ 8. Furthermore, although Kimura ‘352 does not specifically disclose “the third insulator having a third thickness equal to the first thickness in a third direction from the third gate to the first cathode; the fourth insulator having a fourth thickness equal to the second thickness in a fourth direction from the fourth gate; the fifth insulator having a fifth thickness equal to the first thickness in a fifth direction from the fifth gate to the third cathode; and the sixth insulator having a sixth thickness equal to the first thickness in a sixth direction from the sixth gate to the fourth cathode”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed ranges and values for the first, second, third and fourth insulator thicknesses of Kimura’s similar features since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272,205USPQ 215 (CCPA 1980) . 07-21-aia AIA Claim s 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura US 2008/0291352 A1 (Kimura ‘352) in view of Hung et al. US 2021/0366846 A1 . Regarding claims 9 and 10, Kimura does not disclose: (claim 9) wherein the first FET comprises a first gate-all- around (GAA) FET, and the second FET comprises a second GAA FET; and (claim 10) wherein the first FET comprises a first FinFET, and the second FET comprises a second FinFET. Hung discloses a publication from a similar field of endeavor in which: (claim 9) wherein the first FET comprises a first gate-all- around (GAA) FET, and the second FET comprises a second GAA FET; and (claim 10) wherein the first FET comprises a first FinFET, and the second FET comprises a second FinFET (para 0017; active devices used in CMOS inverters may include GAA and FINFET devices). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ GAA and FINFET devices as taught by Hung as alternatives to the standard MOSFETs of Kimura to determine CMOS inverter configurations since such transistor devices are common knowledge in the industry specifically when scaling down circuitry . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 19-36 are allowed. 13-03 AIA The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations of claim 19 stating “a first diffusion region” and “second diffusion region” in the substrate and their respective configurations relative to the first/second varactors, first/second FETs and first/second gate structures; and of claim 34 stating “a first diffusion region” and “second diffusion region” in the substrate and their respective configurations relative to the first/second anode, first/second cathode, third/fourth terminal, first/second gate structures and first/second gates. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893 Application/Control Number: 18/529,087 Page 2 Art Unit: 2893 Application/Control Number: 18/529,087 Page 3 Art Unit: 2893 Application/Control Number: 18/529,087 Page 4 Art Unit: 2893 Application/Control Number: 18/529,087 Page 5 Art Unit: 2893 Application/Control Number: 18/529,087 Page 6 Art Unit: 2893 Application/Control Number: 18/529,087 Page 7 Art Unit: 2893 Application/Control Number: 18/529,087 Page 8 Art Unit: 2893
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