DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Group I (Claims 1-13) in the reply filed on February 10th, 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Fig. 2A of LILAK et al. (Pub. No.: US 2022/0102346 A1), hereinafter as Embodiment 1 of LILAK in view of Liang et al. (Pub. No.: US 2024/0128267 A1), hereinafter as Liang and further in view of Fig. 4A of LILAK et al. (Pub. No.: US 2022/0102346 A1), hereinafter as Embodiment 4 of LILAK.
Regarding claim 1, Embodiment 1 of LILAK discloses a semiconductor structure in Figs. 2A comprising: a standard logic cell comprising: a top field effect transistor (FET) (forksheet transistor 220D) comprising a plurality of top channels (upper channels 206), wherein the plurality of top channels are in contact with a first gate cut region (first backbone 210B) (see [0046]); and a bottom FET (forksheet transistor 220B) comprising a plurality of bottom channels (lower channels 206), wherein the plurality of bottom channels are in contact with a second dielectric liner of a second gate cut region (second backbone 210A), wherein the top FET and the bottom FET share a gate, and wherein the top FET is disposed in an offset position with respect to the bottom FET (misaligned by space M) (see Fig. 2A and [0051]).
Embodiment 1 of LILAK fails to disclose wherein the plurality of top channels are in contact with a first dielectric liner of the first gate cut region and wherein the plurality of bottom channels are in contact with a second dielectric liner of the second gate cut region and wherein the top FET and the bottom FET share a gate.
Liang discloses a semiconductor structure in Fig. 27 comprising a first plurality of channels (left stack of epitaxial layers 102) are in contact with a first dielectric liner (left liner 510) of a first gate cut region (left dielectric wall 520) (see [0011], [0016-0017]); and a second plurality of channels (right stack of epitaxial layers 102) are in contact with a second liner (right liner 510) of a second gate cut region (right dielectric wall 520).
By incorporating a first dielectric liner (left liner 510) and a second dielectric liner (right liner 510) of Liang into the semiconductor structure of Embodiment 1 of LILAK for reciting wherein the plurality of top channels are in contact with a first dielectric liner of the first gate cut region and wherein the plurality of bottom channels are in contact with a second dielectric liner of the second gate cut region as recited in claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporating the first dielectric liner the second dielectric liner of Liang into the semiconductor structure of Embodiment 1 of LILAK because having the modified structure would provide more uniform structure for the gate cut regions and reduce defects in the semiconductor device.
The combination of Embodiment 1 of LILAK and Liang fails to disclose wherein the top FET and the bottom FET share a gate.
Embodiment 4 LILAK discloses a semiconductor structure wherein a top FET (forksheet transistor 220D) and a bottom FET (forksheet transistor 220B) share a gate (gate electrode 413 of transistor 420D and gate electrode 413 of transistor 420B connecting by interconnect 415 having the same material and making a share gate structure) (see Fig. 4B and [0061-0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the top FET and the bottom FET of the Embodiment 1 of LILAK to have a share gate as same as the Embodiment 4 of LILAK because the modified structure would provide a reliable integrate circuit with common gate structure for application of making inverter or amplifier.
Regarding claim 3, the combination of Embodiment 1 of LILAK, Liang and Embodiment 4 of LILAK discloses the semiconductor structure of claim 1, wherein the first gate cut region comprises the first dielectric liner (material of liner 510 of Liang includes SiN) and a dielectric fill (material of backbone 210 not conducting) (see LILAK, Fig. 2A, [0046] and Liang, Fig. 20A-20B, [0016]), wherein the first dielectric liner comprises a first dielectric that is different than the dielectric fill (see [0016]).
Regarding claim 4, the combination of Embodiment 1 of LILAK, Liang and Embodiment 4 of LILAK discloses the semiconductor structure of claim 1, wherein the second gate cut region comprises the second dielectric liner (right liner 510 of Liang) and a deep via (backbone 210A) (see LILAK, Fig. 2A and Liang, Fig. 27).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over LILAK et al. (Pub. No.: US 2022/0102346 A1), hereinafter as LILAK and further in view of Liang et al. (Pub. No.: US 2024/0128267 A1), hereinafter as Liang, applied to claim 1 above and further in view of LEE et al (Pub. No.: US 2024/0413251 A1), hereinafter as LEE.
Regarding claim 2, the combination of Embodiment 1 of LILAK, Liang and Embodiment 4 of LILAK discloses the semiconductor structure of claim 1, further comprising: a bonding layer (insulating layer 214 of LILAK), wherein the bonding layer is in contact with the first dielectric liner (liner 510 of Liang incorporating into the semiconductor structure of LILAK for surrounding backbone 210-A), and wherein a gate metal (gate metal 213) is disposed between the bonding layer (insulating layer 214) and the second dielectric liner (liner 510 of Liang) (see Fig. 2A of LILAK and Fig. 27).
The combination of Embodiment 1 of LILAK, Liang and Embodiment 4 of LILAK fails to disclose the bonding layer is made of oxide.
LEE discloses a semiconductor structure comprising a bonding layer (insulating film 180) is bonding oxide layer (silicon oxide) (see Fig. 12 and [0109-0110]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the material of the bonding layer of LEE for forming the bonding layer of Embodiment 1 of LILAK and Liang from silicon oxide because it is conventional to use silicon oxide as bonding layer with low manufacturing cost and easy manufacturing.
Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Wherein the deep via connects a bottom source / drain (S/D) epitaxial to a frontside interconnect as recited in claim 5.
Wherein the deep via connects a top S/D epitaxial to a backside interconnect as recited in claim 6.
Wherein the first gate cut region separates a top merged active device into two top active devices, and wherein the first gate cut region separates a bottom merged active device into two bottom active devices as recited in claim 7.
Claims 8-13 are allowed over prior art of record.
The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following: wherein the first gate cut region separates a top merged active device into two top active devices, and wherein the first gate cut region separates a bottom merged active device into two bottom active devices as recited in claim 8. Claims 9-13 depend on claim 8, and therefore also include said claimed limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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