DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed June 22, 2026.
Claims 1-20 are pending. Claims 1, 6 and 17 are amended. Claims 1, 6 and 17 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on January 8, 2024.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-9 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (U.S. 2018/0012867; hereinafter “Kim”).
Regarding independent claim 1, Kim discloses a memory device (Fig. 2) comprising:
a buffer die (Figs. 2 and 3C-3D: 150 and 250c-d) comprising a first interface circuit (Fig. 2: 151 and Fig. 3C: 251c) and a second interface circuit (Fig. 2: 152 and Fig. 3C: 252c) configured to communicate with an external device (interfaces 251c and 252c communicate with an external memory controller and an external power supply or a power management integrated circuit (PMIC) through SB and PB, see Fig. 3C, see also page 5, par. 0052), the first interface circuit providing a first interface between the buffer die and the external device (Fig. 3C: 251c provides SB to exchange signal with an external memory controller) and the second interface circuit providing a second interface between the buffer die and the external device (Fig. 3C: 252c provides PB to receive power from an external power supply or a power management integrated circuit (PMIC)), wherein the first interface circuit (Fig. 2: 151) is configured to activate to transmit data through the first interface (Fig. 1: DQ) responsive to a first selection signal (see page 4, par. 0048), and the second interface circuit (Fig. 2: 152) is configured to activate to transmit data through the second interface (see page 5, par. 0052; PB can be connected to a power management integrated circuit (PMIC), PMIC send data signals through the second interface 252c) responsive to a second selection signal (see page 4, par. 0048); and
a memory die stack (Fig. 2: 110-140) mounted on the buffer die (Fig. 2: 150) and including a plurality of memory dies (see page 3, par. 0033), wherein the plurality of memory dies are electrically connected to the first interface circuit (Fig. 2: 151) and the second interface circuit (Fig. 2: 152),
wherein the first selection signal and the second selection signal are received from a memory controller external to the memory device (Fig. 2: MC, see also pages 4-5, par. 0048-0050).
Regarding claim 2, Kim discloses the limitations with respect to claim 1.
As discussed above, Kim’s memory device is substantially identical in structure to the claimed “memory device,” where the differences reside only in the remaining limitations relating to function of “process, in parallel, data transmitted to and received from the plurality of memory dies.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Kim’s memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 3, Kim discloses the limitations with respect to claim 2.
Furthermore, Kim discloses wherein, after the data is processed in parallel, the memory device is configured to transmit, to the memory controller, first interface circuit data or second interface circuit data based on the first selection signal and the second selection signal (see page 4-5, par. 0048-0050).
Regarding independent claim 6, Kim discloses a memory device (Fig. 2) comprising:
a buffer die (Figs. 2 and 3C-3D: 150 and 250c-d) comprising a first interface circuit (Fig. 2: 151 and Fig. 3C: 251c) and a second interface circuit (Fig. 2: 152 and Fig. 3C: 252c) configured to communicate with an external device (interfaces 251c and 252c communicate with an external memory controller and an external power supply or a power management integrated circuit (PMIC) through SB and PB, see Fig. 3C, see also page 5, par. 0052), the first interface circuit providing a first interface between the buffer die and the external device (Fig. 3C: 251c provides SB to exchange signal with an external memory controller) and the second interface circuit providing a second interface between the buffer die and the external device (Fig. 3C: 252c provides PB to receive power from an external power supply or a power management integrated circuit (PMIC)), wherein the first interface circuit (Fig. 2: 151) is configured to activate to transmit data through the first interface (Fig. 1: DQ) responsive to a first selection signal (see page 4, par. 0048), and the second interface circuit (Fig. 2: 152) is configured to activate to transmit data through the second interface (see page 5, par. 0052; PB can be connected to a power management integrated circuit (PMIC), PMIC send data signals through the second interface 252c) responsive to a second selection signal (see page 4, par. 0048); and
a memory die stack (Fig. 2: 110-140) mounted on the buffer die (Fig. 2: 150) and including a plurality of memory dies (see page 3, par. 0033), wherein the plurality of memory dies are electrically connected to the first interface circuit (Fig. 2: 151) and the second interface circuit (Fig. 2: 152).
As discussed above, Kim’s memory device is substantially identical in structure to the claimed “memory device,” where the differences reside only in the remaining limitations relating to function of “wherein, which of the first interface circuit and the second interface circuit is activated to communicate with an external memory controller is based on whether the first selection signal is fixed to a first voltage level or a second voltage level different from the first voltage level and whether the second selection signal is fixed to the first voltage level or the second voltage level.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Kim’s memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 7, Kim discloses the limitations with respect to claim 6.
Furthermore, Kim discloses a redistribution layer of the buffer die (see page 5, par. 0056).
As discussed above, Kim’s memory device is substantially identical in structure to the claimed “memory device,” where the differences reside only in the remaining limitations relating to function of “provide the first voltage level or the second voltage level of the first selection signal and the second selection signal.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Kim’s memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 8, Kim discloses the limitations with respect to claim 6.
Furthermore, Kim discloses an interposer of a semiconductor package comprising the memory device (see page 7, par. 0075).
As discussed above, Kim’s memory device is substantially identical in structure to the claimed “memory device,” where the differences reside only in the remaining limitations relating to function of “provide the first voltage level or the second voltage level of the first selection signal and the second selection signal.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Kim’s memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 9, Kim discloses the limitations with respect to claim 6.
As discussed above, Kim’s memory device is substantially identical in structure to the claimed “memory device,” where the differences reside only in the remaining limitations relating to function of “process, in parallel, data transmitted to and received from the plurality of memory dies.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Kim’s memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding independent claim 17, Kim discloses a memory device (Fig. 2) comprising:
a buffer die (Figs. 2 and 3C-3D: 150 and 250c-d) comprising a first interface circuit (Fig. 2: 151 and Fig. 3C: 251c) and a second interface circuit (Fig. 2: 152 and Fig. 3C: 252c) configured to communicate with an external device (interfaces 251c and 252c communicate with an external memory controller and an external power supply or a power management integrated circuit (PMIC) through SB and PB, see Fig. 3C, see also page 5, par. 0052), the first interface circuit providing a first interface between the buffer die and the external device (Fig. 3C: 251c provides SB to exchange signal with an external memory controller) and the second interface circuit providing a second interface between the buffer die and the external device (Fig. 3C: 252c provides PB to receive power from an external power supply or a power management integrated circuit (PMIC)), wherein the first interface circuit (Fig. 2: 151) is configured to activate to transmit data through the first interface (Fig. 1: DQ) responsive to a first selection signal (see page 4, par. 0048), and the second interface circuit (Fig. 2: 152) is configured to activate to transmit data through the second interface (see page 5, par. 0052; PB can be connected to a power management integrated circuit (PMIC), PMIC send data signals through the second interface 252c) responsive to a second selection signal (see page 4, par. 0048); and
a memory die stack (Fig. 2: 110-140) mounted on the buffer die (Fig. 2: 150) and including a plurality of memory dies (see page 3, par. 0033), wherein the plurality of memory dies are electrically connected to the first interface circuit (Fig. 2: 151) and the second interface circuit (Fig. 2: 152),
wherein the first selection signal and the second selection signal are generated inside the memory device responsive to an interface selection signal received from a memory controller external to the memory device (Fig. 2: MC, see also pages 4-5, par. 0048-0050).
Regarding claim 18, Kim discloses wherein the buffer die further comprises a decoder circuit configured to receive the interface selection signal and to generate the first selection signal and the second selection signal (see page 3, par. 0035).
Regarding claim 19, Kim discloses the limitations with respect to claim 17.
As discussed above, Kim’s memory device is substantially identical in structure to the claimed “memory device,” where the differences reside only in the remaining limitations relating to function of “process, in parallel, data transmitted to and received from the plurality of memory dies.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Kim’s memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Allowable Subject Matter
Claims 4-5, 10-16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, there is no teaching or suggestion in the prior art of record to provide the recited buffer die further comprises a mode register configured to store an interface mode parameter code indicating a single interface mode or a multi interface mode to set the signal interface mode or the multi interface mode for the first interface circuit and the second interface circuit, in the single interface mode, communication is performed with the memory controller by using the first interface circuit or the second interface circuit, and in the multi interface mode, communication is performed with the memory controller by using both the first interface circuit and the second interface circuit.
With respect to claim 10, there is no teaching or suggestion in the prior art of record to provide the recited buffer die comprises a mode register configured to store an interface mode parameter code indicating a single interface mode or multi interface mode to set the single interface mode or the multi interface mode for the first interface circuit and the second interface circuit, in the single interface mode, communication is performed with the memory controller by using the first interface circuit or the second interface circuit, and in the multi interface mode, communication is performed with the memory controller by using both the first interface circuit and the second interface circuit.
With respect to claim 20, there is no teaching or suggestion in the prior art of record to provide the recited buffer die further comprises a mode register configured to store an interface mode parameter code indicating a single interface mode or a multi interface mode to set the single interface mode or the multi interface mode for the first interface circuit and the second interface circuit, in the single interface mode, communication is performed with the memory controller by using the first interface circuit or the second interface circuit, and, in the multi interface mode, communication is performed with the memory controller by using both the first interface circuit and the second interface circuit.
Response to Arguments
Applicant's arguments filed with respect to independent claims 1, 6 and 17 have been fully considered but they are not persuasive.
With respect to independent claims 1, 6 and 17, Applicant asserts that Kim discloses only a single interface and therefore fails to describe any selection signals that are used to selectively activate different interface circuits to transmit data through a respective interface, see Applicant’s Remarks page 8. This particular remark is not considered persuasive.
After further consideration, Kim discloses in Figure 3C two interface circuits 251c and 252c and each of the interface circuits comprises interfaces SB and PB to communicate to an external device and transmits signals through SB and PB, the rejection has been augmented to address the recent amendments.
Therefore, the above rejections are considered proper and maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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