DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Species I (claims 1-10) in the reply filed on 4/13/26 is acknowledged. The traversal is on the ground(s) that all three species share a common inventive concept, the search burden is minimal and the Examiner alleges the species require different search strategies and search queries but this justification is conclusory. This is not found persuasive because Species II, and Species III require different search strategies that are different than Species I (i.e. claims 1-10, paragraph [0006] of the specification), which requires a boundary between the first active regions and the second active regions which extends in the first direction. Species II (i.e. claims 11-15, paragraph [0007]) requires a liner layer on the device isolation layer and the first and second source/drain patterns, and Species III (i.e. claims 16-20, paragraph [0008]) requires a first and second gate contacts wherein these features are disclosed in their respective species that require different search strategies and searches in other subclasses.
The requirement is still deemed proper and is therefore made FINAL.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 4/13/26.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 thru 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In lines 6-7 of claim 1, the applicant states “a device isolation layer on the substrate in a
trench between the first active region and the second active regions;” and then in lines 18-19 states “wherein the device isolation layer comprises a protrusion structure between adjacent ones of the first active regions,”; however, it is unclear how the device isolation layer can be “in a trench” and then also be “a protrusion structure.” For example, in FIG. 3D, the applicant shows the protrusion structure MS being a part of the device isolation layer ST, but it does not appear that the protrusion structure MS is actually a different structure, but only an arbitrary area of the same device isolation layer ST, and does not “protrude” (i.e. stays under a top surface of the device isolation layer ST), as implied by the term “protrusion” in the limitation “protrusion structure.” Appropriate clarification and/or correction are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In view of the 112 rejection above, claim(s) 1 thru 3, 5, 6, 8, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0059558 A1 in view of Bae et al. US 2021/0391464 A1. Kim discloses (see, for example, FIG. 1, and 2) a semiconductor device comprising a substrate 100 that comprises first active regions 105A/105C and second active regions 105B/105D, wherein the first active regions 105A/105C are arranged along a first direction (i.e. y-direction or vertical direction), wherein the second active regions 105B/105D are arranged along the first direction, and wherein a boundary (i.e. between the first active region 105A and second active region 105B towards the right side of FIG. 1) 146 between the first active regions 105A/105C and the second active regions 105B/105D extends in the first direction; a device isolation layer 110 on the substrate 100 in a trench 110t between the first active regions 105A/105C and the second active regions 105B/105D; a first channel pattern 105A and a first source/drain pattern 120C/120B on each of the first active regions 105A/105C; a second channel pattern 105B and a second source/drain pattern 120D on each of the second active regions 105B/105D; a first gate electrode 134B on the first channel pattern 105A; a second gate electrode 134C on the second channel pattern 105B, a plurality of active contacts 144 on the first source/drain pattern 120C/120B on each of the first active regions 105A/105C and the second source/drain pattern 120D on each of the second active regions 105B/105D, wherein the device isolation layer comprises a protrusion structure 146/116 between adjacent ones of the first active regions 105A/105C, and wherein the protrusion structure 146/116 is adjacent to the boundary. Kim does not disclose the first gate electrode extends in the first direction across the first active regions, and the second gate electrode extends in the first direction across the second active regions. However, Bae discloses (see, for example, FIG. 1) a semiconductor device comprising gate electrodes GL that extend over multiple active regions in a first direction. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first gate electrode extends in the first direction across the first active regions, and the second gate electrode extends in the first direction across the second active regions in order to have a single continuous gate electrode that crosses multiple active regions, which eliminates the need to manufacture multiple gates, and thereby improves manufacturing uniformity and circuit density.
Regarding claim 2, see, for example, FIG. 1 wherein Kim discloses the protrusion structure 146 having a bar shape that extends in a second direction intersecting the first direction.
Regarding claim 3, see, for example, FIG. 1 wherein Kim discloses the protrusion structure 146 being a region of the device isolation layer which extends in a vertical direction, and wherein the protrusion structure has a planar top surface.
Regarding claim 5, see for example, FIG. 1 wherein Kim discloses a top surface of the protrusion structure 116 being at a first level, wherein a top surface of the device isolation layer below the first gate electrode 134B being at a second level. Kim in view of Bae does not specifically disclose a difference between the first level and the second level being in a range of greater than about 0 nm and less than about 20 nm; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a difference between the first level and the second level being in a range of greater than about 0 nm and less than about 20 nm in order to prevent interference while minimizing the size of the device, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 6, Kim in view of Bae does not specifically each of the first active regions being one of an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) region and a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) region, and wherein each of the second active regions being another of the NMOSFET region and the PMOSFET region, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have each of the first active regions being one of an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) region and a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) region, and wherein each of the second active regions being another of the NMOSFET region and the PMOSFET region in order to build more robust devices such as complementary transistors for high power consumption and increased scalability as is well known in the art.
Regarding claim 8, see, for example, FIG. 2 wherein Kim discloses a liner layer 114 on the device isolation layer, the first source/drain pattern 120C/120B on each of the first active regions 105A/105C and the second source/drain pattern 120D on each of the second active regions 105B/105D, wherein the liner layer 114 directly covers the protrusion structure 116.
Regarding claim 10, see, for example, FIG. 2 wherein Kim discloses the protrusion structure 146/116 comprises a first protrusion structure 146 and a second protrusion structure 116 that are spaced apart from each other in the first direction, and wherein a width in the first direction of the first protrusion structure 146 is different from a width in the first direction of the second protrusion structure 116.
Claim(s) 4, 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0059558 A1 in view of Bae et al. US 2021/0391464 A1 as applied to claims 1-3, 5, 6, 8, and 10 above, and further in view of Komori US 2002/0064912 A1. Kim in view of Bae does not disclose the device isolation layer further comprises a recess region between the protrusion structure and the first source/drain pattern. However, Komori discloses (see, for example, FIG. 15) a semiconductor device comprising a device isolation layer 21 further comprising a recess region 71 next to the active region 11. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the device isolation layer further comprises a recess region between the protrusion structure and the first source/drain pattern in order to increase the withstand voltage of the device along the junction, diminishing parasitic capacitance between the gate and the semiconductor substrate, and reducing stress and kinetics at the boundary surface.
Regarding claim 7, see, for example, FIG. 15 wherein Komori discloses the recessed top surface 21 being lower than a level of a top surface of the protrusion structure.
Regarding claim 9, see, for example, FIG. 2 wherein Kim discloses the first gate electrode comprises a pair of first gate electrodes 134B/134A adjacent to each other and on the device isolation layer 110, wherein the second gate electrode 134C comprises a pair of second gate electrodes adjacent to each other and on the device isolation layer 110, wherein the protrusion structure 146/116 being provided on the device isolation layer 110 between the pair of first gate electrodes 134B/134A. Kim in view of Bae does not disclose a recess region being provided on the device isolation layer between the pair of second gate electrodes. However, Komori discloses (see, for example, FIG. 15) a recess region 71 being provided on the device isolation layer 21. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a recess region in order to increase the withstand voltage of the device along the junction, diminishing parasitic capacitance between the gate and the semiconductor substrate, and reducing stress and kinetics at the boundary surface.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
May 19, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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