Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mimoto et al, US 6326693 B1 in view of JP 2004079693 A and in further view of JP 2005217071 A
Mimoto teaches:
What is claimed is:
1. A semiconductor device, comprising:
a core area comprising a cell array (figure 14);
a pad area (56, 57) surrounding the core area;
a plurality of power lines (4, 5) on the pad area;
Mimoto fails to teach:
a plurality of alignment marks on the pad area,
wherein each of the plurality of alignment marks are configured to be electrically
connected to one power line among the plurality of power lines.
JP 2004079693 A teaches:
a plurality of alignment marks (24) on the pad area (Figure 2),
JP 2005217071 A teaches:
wherein each of the plurality of alignment marks (43) are configured to be electrically connected to one power line among the plurality of power lines. Figure 7, para 44.
Therefore. it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because alignment mark are conventionally used in the art to align the chips. And also further the potential of any alignment mark can be fixed by being electrically connected to a power supply line or a GND line through a wiring layer or a bump on the chip. By fixing the potential of the alignment mark, noise during operation of the multichip semiconductor device can be reduced. (071, para 44)
JP 2004079693 A also teaches:
2. The semiconductor device of claim 1, wherein the alignment mark (24) is disposed in at least one or more corner area of the pad area. (Figure 2).
Mimoto further teaches:
14. A semiconductor device, comprising:
a core area comprising a cell area; (figure 14)
a pad area (56,57) surrounding the core area;
a plurality of insulating layers in the pad area; (not labeled Figure 6)
a plurality of power lines (4, 5) between the plurality of insulating layers;
wherein the uppermost power line comprises:
a first power line (56) disposed adjacent to the core area; and
a second power line (57) disposed farther from the core area than the first power line. (figure 14)
Mimoto fails to teach
a plurality of alignment marks on the uppermost power line among the plurality of
power lines,
and
wherein each of the plurality of alignment marks is configured to be electrically
connected to one of the first power line and/or the second power line.
JP 2004079693 A teaches:
a plurality of alignment marks (24) on the pad area (Figure 2),
JP 2005217071 A teaches:
wherein each of the plurality of alignment marks (43) are configured to be electrically connected to one power line among the plurality of power lines. Figure 7, para 44.
Therefore. it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because alignment mark are conventionally used in the art to align the chips. And also further the potential of any alignment mark can be fixed by being electrically connected to a power supply line or a GND line through a wiring layer or a bump on the chip. By fixing the potential of the alignment mark, noise during operation of the multichip semiconductor device can be reduced. (071, para 44)
JP 2005217071 A teaches
15. The semiconductor device of claim 14, wherein
each of the plurality of insulating layers comprises a via (2) (figure 1), and
the plurality of power lines are electrically connected to each other through the plurality of vias. (figure 7)
JP 2004079693 A teaches:
16. The semiconductor device of claim 14, wherein the alignment mark is disposed in at least one or more corner area of the pad area.
Claim(s) 3, 4 and 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mimoto et al, US 6326693 B1 in view of JP 2004079693 A and in view of JP 2005217071 A as applied to claims 1 and 14 above, and in further view of CN 113130463 B
The above references fail to teach:
3. The semiconductor device of claim 1, wherein the alignment mark is disposed on the one power line among the plurality of power lines and is configured to be electrically connected to the one power line.
4. The semiconductor device of claim 1, wherein the alignment mark is disposed on the plurality of power lines and is configured to be electrically connected to one power line of the plurality of power lines.
17. The semiconductor device of claim 14, wherein the alignment mark is disposed on one of the first power lines and the second power line, and is configured to be electrically connected to the one power line.
18. The semiconductor device of claim 14, wherein the alignment mark is disposed on the first power line and the second power line, and is configured to be electrically connected to one of the first power line and/or the second power line.
CN 113130463 B teaches:
the power signal auxiliary line and the alignment mark are set in the same layer, (see Figure 3)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the above references, because it can realize the power supply signal auxiliary line and the alignment mark formed in a patterning process, the current uniformity of the power supply signal line is improved. (CN 113130463 B)
Claim(s) 5, 6, 7, 10 - 13 and 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mimoto et al, US 6326693 B1 in view of JP 2004079693 A and in view of JP 2005217071 A as applied to claims 1 and 14 above, and in further view of Kim et al, US 20080284048 A1
The above references fail to teach:
5. The semiconductor device of claim 1, wherein the alignment mark comprises a power pad, a pad open, and a bump.
6. The semiconductor device of claim 5, comprising:
an insulating layer comprising the pad open,
wherein
the power pad is a part of one power line among the plurality of power lines,
the pad open is located on the power pad, and
the bump is configured to contact the power pad through the pad open.
7. The semiconductor device of claim 1, wherein each of the plurality of power lines comprises:
a first power line disposed adjacent to the core area; and
a second power line disposed farther from the core area than the first power line, and
wherein the alignment mark comprises a power pad, a pad open, and a bump.
10. The semiconductor device of claim 7, comprising:
a first power pad configured to connect the first power line in at least one or more corner area of the pad area from a first direction to a second direction perpendicular to the first direction; and
a second power pad configured to connect the second power line in the corner area from
the first direction to the second direction,
wherein
the pad open is located on the first power pad, and
the bump is configured to contact the first power pad through the pad open.
11. The semiconductor device of claim 10, wherein the bump is disposed on the first power pad and the second power pad.
12. The semiconductor device of claim 7, comprising:
a first power pad configured to connect the first power line in at least one or more corner area of the pad area from a first direction to a second direction perpendicular to the first direction; and
a second power pad configured to connect the second power line in the corner area from the first direction to the second direction,
wherein the pad open is located on the second power pad, and
the bump is configured to contact the second power pad through the pad open.
13. The semiconductor device of claim 12, wherein the bump is disposed on the first power pad and the second power pad.
19. The semiconductor device of claim 14, wherein the alignment mark comprises a power pad, a pad open, and a bump.
20. The semiconductor device of claim 14, wherein
the alignment mark comprises a power pad, a pad open, and a bump,
the uppermost insulating layer among the plurality of insulating layers comprises the pad open,
the power pad is a part of one of the first power line and the second power line,
the pad open is located on the power pad, and
the bump is configured to contact the power pad through the pad open.
Kim teaches:
wherein the alignment mark (14a) comprises a power pad (14a), a pad open (15a), and a bump (18A).
While Mimoto teaches:
The power line 5 is formed in a manner that the power line 4 is moved in an imaginary diagonal line passing opposing corner (for example, P1 and P2) of the rectangle of the core 1. Both the power lines 4 and 5 run through a plurality of interconnection layers of a semiconductor substrate, and end points of sides of the power lines are connected through interlayer interconnections. More specifically, in this embodiment, x-direction side lines 4a, 5a, 4c and 5c are formed in the first layer and y-direction side lines 4b, 5b, 4d and 5d are formed in the second layer which is, e.g., an upper layer of the first layer. (para 4)
power lines 4 and 5 connected to V.sub.DD and V.sub.SS, respectively, are connected to not only the core circuit 1 but also to a logic circuit 6 via reinforcing lines 31-34 and 41-44 to supply the power thereto. By employing such arrangement, the core circuit 1 and the logic circuit 6 are respectively connected via the common lines 4a, 4b, 5a and 5b to V.sub.DD and V.sub.SS. (para 43)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the above references, because the interconnection area between the core circuit and the logic circuit is decreased. (para 43, Mimoto)
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the above references fail to teach:
8. The semiconductor device of claim 7, wherein
at least one or more corner area of the pad area comprises a disconnection area where the second power line is disconnected, and
the power pad is configured to extend from the first power line to the disconnection area.
9. The semiconductor device of claim 7, wherein
at least one or more corner area of the pad area comprises a disconnection area where the first power line is disconnected, and
the power pad is configured to extend from the second power line to the disconnection area.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893