Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-4 and 9-13 are rejected under 35 U.S.C. 102(a1) as being anticipated by Cho et al. (US 10,361,205; hereinafter Cho).
Regarding claim 1, Cho, in figs. 1 & 2A, discloses a semiconductor device comprising: a substrate 102 including a plurality of active regions AR, and defining a plurality of first gate trenches T1a and a plurality of second gate trenches T2 crossing the plurality of active regions AR and extending in a first horizontal direction (fig. 1, WL direction); a plurality of gate structures including a plurality of first gate structures 114a within the plurality of first gate trenches T1a and a plurality of second gate structures 124 within the plurality of second gate trenches T2; a bit line structure BL crossing the plurality of gate structures and extending in a second horizontal direction (fig. 1, BL direction) that intersects the first horizontal direction (fig. 1, WL direction); and a contact plug 310 on a side surface of the bit line structure BL, wherein, when viewed in plan view, an area of at least some of the plurality of first gate structures 114a is different from an area of at least some of the plurality of second gate structures 124 (the second gate structures 124 form a WL, and the first gate structures 114a form another WL adjacent to the WL).
Regarding claim 2, Cho discloses wherein a depth of at least some of the plurality of first gate structures 114a is different from a depth of at least some of the plurality of second gate structures 124 (fig. 2A).
Regarding claim 3, Cho discloses wherein a length of each of the first gate structures 114a in the first horizontal direction (fig. 1, WL direction) is different from a length of each of the second gate structures 124 in the first horizontal direction (fig. 2A).
Regarding claim 4, Cho discloses wherein centers of the plurality of first gate structures 114a in the first horizontal direction (fig. 1, WL direction) are displaced from centers of the plurality of second gate structures 124 in the first horizontal direction (fig. 2A).
Regarding claim 9, Cho discloses wherein a horizontal width of the plurality of first gate structures 114a in the second horizontal direction is different from a horizontal width of the second gate structure 124 in the second horizontal direction (fig. 2A).
Regarding claim 10, Cho discloses wherein lengths of the plurality of first gate structures 114a in the first horizontal direction are different from lengths of the plurality of second gate structures 124 in the first horizontal direction (fig. 2A).
Regarding claim 11, Cho discloses wherein respective active regions AR overlap one of the plurality of first gate structures 114a and one of the plurality of second gate structures 124 in a vertical direction (figs. 1 & 2A).
Regarding claim 12, Cho discloses wherein the substrate further includes a device isolation layer STI between the plurality of active regions AR, and the device isolation layer STI includes a first region and a second region deeper than the first region (fig. 2B).
Regarding claim 13, Cho discloses wherein a lower surface of each of the first gate structures 114a includes a first portion contacting the first region of the device isolation layer STI and a second portion contacting the second region of the device isolation layer STI and lower than the first portion (fig. 2B).
Allowable Subject Matter
2. Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
3. Claims 14-20 are allowed.
The following is an examiner's statement of reason for allowance: the prior art of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of " wherein the plurality of first gate structures are alternately arranged with the plurality of second gate structures in the second horizontal direction, and the plurality of first gate structures have a length different from a length of the plurality of second gate structures in at least one direction among the first horizontal direction, the second horizontal direction, and a vertical direction” (claim 14); or “wherein the plurality of first gate structures are alternately arranged with the plurality of second gate structures in the second horizontal direction, and first and second ends of the plurality of first gate structures that are spaced apart from each other in the first horizontal direction are arranged in a zigzag pattern with first and second ends of the respective second gate structures that are spaced apart from each other in the first horizontal direction” (claim 19) as instantly claimed and in combination with the remaining elements.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance".
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818