DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 18 August 2026 with respect to the rejections of claims 1-11 have been fully considered and are persuasive. However, upon further consideration of the amendments to the claims, new grounds of rejection for claims 1-8 are made in view of newly found prior art in combination with the previous prior art and claims 9-11 are now considered allowable.
Applicant’s arguments filed 18 August 2026 with respect to the objections to claims 3 and 10 have been considered, and in view of amendments, are persuasive. The objections to claims 3 and 10 are therefore withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Mizukami et al. US 20200091334 in view of Nakano US 20240282749.
Regarding claim 1, Mizukami discloses a semiconductor device, comprising:
a first electrode (figure 1, 14 [0037]);
a first semiconductor layer (figure 1, 24/26 [0038]) connected to the first electrode,
the first semiconductor layer including silicon and carbon ([0038] discloses that all the layers comprising layer 10, including layer 24/26, comprise silicon carbide),
the first semiconductor layer being of a first conductivity type (figure 1, layer 24/26 has an n-type conductivity type [0038]) ;
a second semiconductor layer located on a portion of the first semiconductor layer (figure 1/2, layer 28/32, is located on a portion of the first semiconductor layer 24/26),
the second semiconductor layer contacting the first semiconductor layer (see figure 1, where second semiconductor layer 28/32 contacts first semiconductor layer 24/26) and including silicon and carbon (paragraph [0038] discloses that region 28/32 is a silicon carbide region, as it is a part of silicon carbide layer 10),
the second semiconductor layer being of a second conductivity type (paragraph [0038] discloses that region 28/32 is a p-type region);
a third semiconductor layer located on a first portion of the second semiconductor layer (figure 1 shows that third semiconductor layer 30 is located on a first portion of the second semiconductor layer 28/32),
the third semiconductor layer including silicon and carbon (paragraph [0038] discloses that third semiconductor layer 30 is composed of silicon carbide, as it is a component of silicon carbide layer 10),
the third semiconductor layer being of the first conductivity type (paragraph [0038] discloses that third semiconductor layer 30 has n-type conductivity);
a fourth semiconductor layer located on a second portion of the second semiconductor layer (Figure 1 shows a fourth semiconductor layer 38 [0038], located on a second portion of the second semiconductor layer 28/32),
the fourth semiconductor layer including silicon and carbon (paragraph [0038] discloses that region 38, as a component of layer 10, is silicon carbide),
the fourth semiconductor layer being of the second conductivity type (figure 10 shows layer 38 has p+-type conductivity),
the fourth semiconductor layer having a higher carrier concentration than the second semiconductor layer (Paragraph [0065] discloses that the fourth semiconductor region 38 has a p-type impurity concentration between 5×1018 cm.−3 and 1×1021 cm.−3; and paragraph [0057] discloses that the carrier concentration of the second semiconductor layer 28/32 is for part 28 between 5×1016 cm.−3 and 5×1018 cm.−3 and for part 32 between 5×1017 cm.−3 and 1×1019 cm.−3 . Therefore, the fourth semiconductor layer 38, has a higher carrier concentration than the second semiconductor layer 28/32 as a whole, averaging the carrier concentrations of each of the sublayers over the total area.)
a fifth semiconductor layer located on a third portion of the second semiconductor layer (figure 3, shows that layer 34a/34b is located on layer 28/32 - notice that figure 3 is a different cross section of the first embodiment [0029-0035]) ,
the fifth semiconductor layer including silicon and carbon (paragraph [0038] discloses that layer 34a/34b is silicon carbide)
the fifth semiconductor layer being of the second conductivity type (figure 3 shows that layer 34a/34b has p+-type conductivity),
the fifth semiconductor layer having a higher carrier concentration than the second semiconductor layer ( Paragraph [0070] discloses that the p-type impurity concentration of the regions 32a/32b is higher than the p-type impurity concentration of region 28, while paragraphs [0070 and 0078] disclose that fifth semiconductor layer 34a/34b and the second region of the second semiconductor 32a/32b have similar carrier concentrations of between 5×1017 cm.−3 and 1×1019 cm.−3 . Therefore, the fifth semiconductor layer 34a/34b has a higher carrier concentration than the second semiconductor layer 28/32 as a whole, averaging the lower carrier concentration of region 28 with the similar-to-area-34 carrier concentration over the full area of 28/32 .),
PNG
media_image1.png
836
696
media_image1.png
Greyscale
a length in a second direction (the direction designated “second direction” by Mizukami) of the fifth semiconductor layer (figure 1, 34a/34b) being greater than a length in the second direction of the fourth semiconductor layer (38) the second direction crossing a first direction (the direction designated “third direction” by Mizukami), the first direction being from the first electrode toward the first semiconductor layer (Figure 1 shows that the length of layer 34a/34b in the first direction, ‘third direction’ of Mizukami is greater than the length of layer 38 in the same direction);
a second electrode (16a) facing, via an insulating film (18a), a portion of the second semiconductor layer (28/32) located between the first semiconductor layer and the third semiconductor layer (annotated figure 1shows that second electrode 16a faces, via insulating film 18a, a portion of the second semiconductor layer, indicated by the circle, located between the first semiconductor layer and the third semiconductor layer, as indicated by the arrow.)
a third electrode connected to the third, fourth, and fifth semiconductor layers (figure 3 discloses source electrode 12 connected to the third, fourth, and fifth semiconductor layers (paragraph [0094] discloses that electrode 12 is connected to layers 30 and 38, and 34a/34b is electrically connected to 12 through region 32a/32b [0079]).
Mizukami lacks a metal film connected to the third electrode, the metal film being located in a region that includes a region directly above the fifth semiconductor layers and the metal film being located on a part, but not an entirety, of the third electrode.
However, Nakano et al. US 20240282749 discloses a semiconductor device (figure 2, device 1A) with protective metal film (75, [0165-0167]) over the source electrode, located on part, but not all of the source electrode (32), as described in Nakano paragraph [0167].
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to add a protective metal film, similar to Nakano’s layer 75 above Mizukami’s source electrode 12, such that this layer lies in a region directly above the fifth semiconductor layer (Mizukami 34a/34b)s with this metal film being located on a part, but not an entirety, of the third electrode (Mizukami 12), as described by to improve protection of the device.
Regarding claim 2, Mizukami as modified by Nakano discloses the device according to claim 1, wherein the first semiconductor layer includes:
a first layer located on the first electrodeFigure 9 shows that first semiconductor layer 24/26 comprises a first sublayer 24, located on the first electrode 14 and a second sublayer 26, located on sublayer 24) ,
PNG
media_image2.png
791
681
media_image2.png
Greyscale
the second layer having a lower carrier concentration than the first layer (Paragraph [0052] discloses that the carrier concentration of the first layer 24 is between 1018 cm-3 and 1021 cm-3, and paragraph [0054] discloses that the carrier concentration of the second layer 216 is between 4×1014 cm.−3 and 1×1017 cm.−3; therefore, the second layer has a lower carrier concentration than the first layer)
Mizukami as modified by Nakano lacks wherein a shortest distance between an outer edge of the fifth semiconductor layer (34a/34b) and an outer edge of the metal film (the upper metal layer of the third electrode 12, as described in the rejection of claim 1) when viewed along the first direction (Mizukami’s “third direction” in figure 3) is not less than a shortest distance between the first layer (24) and the second semiconductor layer (28/32) in the first direction (Mizukami’s “third direction” in figure 1).
However, regarding changes in size, MPEP 2144.04 IV states:
IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to make the relative dimensions of the device of claim 2 such that distance 1 (see annotated figure 3, where the indicated distance 1 is the shortest distance between an outer edge of 34a/34b and an outer edge of the metal film layer) is not shorter than distance 2 (see annotated figure 3, where the indicated distance 2 is the distance between layer 24 and the layer 28/32a/32b) in order to improve the compactness of the device.
Regarding claim 3, Mizukami as modified by Nakano discloses the device according to claim 1, wherein a plurality of the fifth semiconductor layers is provided (34a, 34b), and layers comprising the plurality of fifth semiconductor layers are separated from each other. (Figure 1 and figure 3 show that layers 34a and 34b, comprising the plurality of fifth semiconductor layers, are separated from one another by other regions 28/32 and 26.)
Regarding claim 4, Mizukami as modified by Nakano discloses the device according to claim 3, wherein the plurality of fifth semiconductor layers is arranged along the second direction (see the arrangement of 34a and 34b along the second direction in figures 1 and 3).
Regarding claim 5, Mizukami as modified by Nakano discloses the device according to claim 4, wherein the plurality of fifth semiconductor layers is arranged also along a third direction, and the third direction crosses a plane parallel to the first and second directions (Figure 2 shows that regions 34a and 34b, which figures 1 and 3 show are located beneath layers 16 in the first direction, Mizukami’s third direction, are also arranged along a third direction, Mizukami’s first direction.)
Regarding claim 6, Mizukami as modified by Nakano discloses the device according to claim 3, wherein the plurality of fifth semiconductor layers is arranged along a third direction, and the third direction crosses a plane parallel to the first and second directions. (Figure 2 shows that regions 34a and 34b, which figures 1 and 3 show are located beneath layers 16 in the first direction, Mizukami’s third direction, are arranged along a third direction, Mizukami’s first direction.)
PNG
media_image3.png
492
418
media_image3.png
Greyscale
Regarding claim 7, Mizukami as modified by Nakano discloses the device according to claim 1, wherein the fifth semiconductor layer includes: a portion extending in the second direction; and a portion extending along a third direction, and the third direction crosses a plane parallel to the first and second directions (These claim limitations lack substance – the fifth semiconductor layer, as an object existing in three-dimensional space, necessarily has portions extending in any three directions, therefore, the fifth semiconductor region of Mizukami 34a/34b includes a portion extending in the second direction and a portion extending along a third direction,)
Regarding claim 8, Mizukami as modified by Nakano discloses the device according to claim 1, further comprising: a metal layer connected to the third electrode, the metal layer being located between the third electrode and a portion of the first semiconductor layer above which the second semiconductor layer is not located, the metal layer forming a Schottky junction with the first semiconductor layer (Paragraph [0083] discloses that the junction between third electrode 12 and the first semiconductor layer 26/24 between regions 28 is Schottky junction, while paragraph [0082] discloses that the electrode 12 may include stacked layers of various metals. Therefore, a lower metal layer of electrode 12 may form a Schottky junction with layer 26, as shown in annotated figure 4).
Allowable Subject Matter
Claims 9 is allowed. Claims 10 and 11, as they are dependent on claim 9, include all the limitations thereof; therefore, they are also allowable.
The following is the examiner’s statement of reasons for allowance:
Regarding claim 9, the prior art does not teach or render obvious, in the combination as claimed, the limitations of claim 9 including a second electrode located on the metal layer and connected to the metal layer; and a metal film connected to the second electrode, the metal film being located in a region that is on the second electrode and includes a region directly above the third semiconductor layer, and the metal film being physically separated from the metal layer with the second electrode therebetween.
After additional search and consideration, the closest prior art is Mizukami et al. US 20200091334, cited in the previous office action, which does not disclose or render obvious in combination with other prior art the limitation added to claim 9 in the amendment, “and the metal film being physically separated from the metal layer with the second electrode therebetween,” in combination with the other limitations of claim 9.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KATRINA WALJESKI-MOSES/ Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights