DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities: “the plurality of fifth semiconductor layers is separated from each other” is grammatically incorrect as the subject of the clause, plurality, is singular, so it cannot be “separated from each other.” A suggested correction is “layers comprising the plurality of fifth semiconductor layers are separated from one another.” Appropriate correction is required.
Claim 10 is objected to because of the following informalities: there is no antecedent basis for its “first direction”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mizukami et al. US 20200091334.
Regarding claim 1, Mizukami discloses a semiconductor device, comprising:
a first electrode (figure 1, 14 [0037]) ;
a first semiconductor layer (figure 1, 24/26 [0038]) connected to the first electrode,
the first semiconductor layer including silicon and carbon ([0038] discloses that all the layers comprising layer 10, including layer 24/26, comprise silicon carbide),
the first semiconductor layer being of a first conductivity type (figure 1, layer 24/26 has an n-type conductivity type [0038]) ;
a second semiconductor layer located on a portion of the first semiconductor layer (figure 1/2, layer 28/32, is located on a portion of the first semiconductor layer 24/26),
the second semiconductor layer contacting the first semiconductor layer (see figure 1, where second semiconductor layer 28/32 contacts first semiconductor layer 24/26) and including silicon and carbon (paragraph [0038] discloses that region 28/32 is a silicon carbide region, as it is a part of silicon carbide layer 10),
the second semiconductor layer being of a second conductivity type (paragraph [0038] discloses that region 28/32 is a p-type region);
a third semiconductor layer located on a first portion of the second semiconductor layer (figure 1 shows that third semiconductor layer 30 is located on a first portion of the second semiconductor layer 28/32),
the third semiconductor layer including silicon and carbon (paragraph [0038] discloses that third semiconductor layer 30 is composed of silicon carbide, as it is a component of silicon carbide layer 10),
the third semiconductor layer being of the first conductivity type (paragraph [0038] discloses that third semiconductor layer 30 has n-type conductivity);
a fourth semiconductor layer located on a second portion of the second semiconductor layer (Figure 1 shows a fourth semiconductor layer 38 [0038], located on a second portion of the second semiconductor layer 28/32),
the fourth semiconductor layer including silicon and carbon (paragraph [0038] discloses that region 38, as a component of layer 10, is silicon carbide),
the fourth semiconductor layer being of the second conductivity type (figure 10 shows layer 38 has p+-type conductivity),
the fourth semiconductor layer having a higher carrier concentration than the second semiconductor layer (Paragraph [0065] discloses that the fourth semiconductor region 38 has a p-type impurity concentration between 5×1018 cm.−3 and 1×1021 cm.−3; and paragraph [0057] discloses that the carrier concentration of the second semiconductor layer 28/32 is for part 28 between 5×1016 cm.−3 and 5×1018 cm.−3 and for part 32 between 5×1017 cm.−3 and 1×1019 cm.−3 . Therefore, the fourth semiconductor layer 38, has a higher carrier concentration than the second semiconductor layer 28/32 as a whole, averaging the carrier concentrations of each of the sublayers over the total area.)
a fifth semiconductor layer located on a third portion of the second semiconductor layer (figure 3, shows that layer 34a/34b is located on layer 28/32 - notice that figure 3 is a different cross section of the first embodiment [0029-0035]) ,
the fifth semiconductor layer including silicon and carbon (paragraph [0038] discloses that layer 34a/34b is silicon carbide)
the fifth semiconductor layer being of the second conductivity type (figure 3 shows that layer 34a/34b has p+-type conductivity),
the fifth semiconductor layer having a higher carrier concentration than the second semiconductor layer ( Paragraph [0070] discloses that the p-type impurity concentration of the regions 32a/32b is higher than the p-type impurity concentration of region 28, while paragraphs [0070 and 0078] disclose that fifth semiconductor layer 34a/34b and the second region of the second semiconductor 32a/32b have similar carrier concentrations of between 5×1017 cm.−3 and 1×1019 cm.−3 . Therefore, the fifth semiconductor layer 34a/34b has a higher carrier concentration than the second semiconductor layer 28/32 as a whole, averaging the lower carrier concentration of region 28 with the similar-to-area-34 carrier concentration over the full area of 28/32 .),
a length in a second direction (the direction designated “second direction” by Mizukami) of the fifth semiconductor layer (figure 1, 34a/34b) being greater than a length in the second direction of the fourth semiconductor layer (38) the second direction crossing a first direction (the direction designated “third direction” by Mizukami), the first direction being from the first electrode toward the first semiconductor layer (Figure 1 shows that the length of layer 34a/34b in the first direction, ‘third direction’ of Mizukami is greater than the length of layer 38 in the same direction);
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a second electrode (16a) facing, via an insulating film (18a), a portion of the second semiconductor layer (28/32) located between the first semiconductor layer and the third semiconductor layer (annotated figure 1shows that second electrode 16a faces, via insulating film 18a, a portion of the second semiconductor layer, indicated by the circle, located between the first semiconductor layer and the third semiconductor layer, as indicated by the arrow.)
a third electrode connected to the third, fourth, and fifth semiconductor layers (figure 3 discloses source electrode 12 connected to the third, fourth, and fifth semiconductor layers (paragraph [0094] discloses that electrode 12 is connected to layers 30 and 38, and 34a/34b is electrically connected to 12 through region 32a/32b [0079]) and,
a metal film connected to the third electrode (Paragraph [0082] discloses that the source electrode 12 of figures 1 and 3 may include stacked layers of various metals. Therefore, the top layer of 12 may be considered to be a metal film connected to the third electrode.)
the metal film being located in a region that includes a region directly above the fifth semiconductor layer and is on the third electrode (The metal film comprising the top layer of the electrode 12 is directly above the fifth semiconductor 34a/34b, as can be seen in figure 3).
Regarding claim 3, Mizukami discloses the device according to claim 1, wherein a plurality of the fifth semiconductor layers is provided (34a, 34b), and the plurality of fifth semiconductor layers is separated from each other. (Figure 1 and figure 3 show that layers 34a and 34b, comprising the plurality of fifth semiconductor layers, are separated from one another by other regions 28/32 and 26.)
Regarding claim 4, Mizukami discloses the device according to claim 3, wherein the plurality of fifth semiconductor layers is arranged along the second direction (see the arrangement of 34a and 34b along the second direction in figures 1 and 3).
Regarding claim 5, Mizukami discloses the device according to claim 4, wherein the plurality of fifth semiconductor layers is arranged also along a third direction, and the third direction crosses a plane parallel to the first and second directions (Figure 2 shows that regions 34a and 34b, which figures 1 and 3 show are located beneath layers 16 in the first direction, Mizukami’s third direction, are also arranged along a third direction, Mizukami’s first direction.)
Regarding claim 6, Mizukami discloses the device according to claim 3, wherein the plurality of fifth semiconductor layers is arranged along a third direction, and the third direction crosses a plane parallel to the first and second directions. (Figure 2 shows that regions 34a and 34b, which figures 1 and 3 show are located beneath layers 16 in the first direction, Mizukami’s third direction, are arranged along a third direction, Mizukami’s first direction.)
Regarding claim 7, Mizukami discloses the device according to claim 1, wherein the fifth semiconductor layer includes: a portion extending in the second direction; and a portion extending along a third direction, and the third direction crosses a plane parallel to the first and second directions (These claim limitations lack substance – the fifth semiconductor layer, as an object existing in three-dimensional space, necessarily has portions extending in any three directions, therefore, the fifth semiconductor region of Mizukami 34a/34b includes a portion extending in the second direction and a portion extending along a third direction,)
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Regarding claim 8, The device according to claim 1, further comprising: a metal layer connected to the third electrode, the metal layer being located between the third electrode and a portion of the first semiconductor layer above which the second semiconductor layer is not located, the metal layer forming a Schottky junction with the first semiconductor layer (Paragraph [0083] discloses that the junction between third electrode 12 and the first semiconductor layer 26/24 between regions 28 is Schottky junction, while paragraph [0082] discloses that the electrode 12 may include stacked layers of various metals. Therefore, a lower metal layer of electrode 12 may form a Schottky junction with layer 26, as shown in annotated figure 4).
Claims 9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hori US 20200091298.
Regarding claim 9, Hori discloses a semiconductor device, comprising:
a first electrode (figure 1, 14 [0016]);
a first semiconductor layer connected to the first electrode (figure 1, layer 20/22 [0020-22]),
the first semiconductor layer including silicon and carbon ([0017] discloses that all the layers comprising layer 10 in figures 1, including layer 20/22, are silicon carbide),
the first semiconductor layer being of a first conductivity type (figure 1, layer 20/22 has an n-type conductivity type [0021-0022]);
a second semiconductor layer located on a portion of the first semiconductor layer (Figure 1 shows second semiconductor layer 24 [0026], located on a portion of the first semiconductor layer 20/22),
the second semiconductor layer contacting the first semiconductor layer (see figure 1, where second semiconductor layer 24 contacts first semiconductor layer 20/22) and including silicon and carbon (paragraph [0017] discloses that region 28 is a silicon carbide region),
the second semiconductor layer being of a second conductivity type (Paragraph [0026] discloses that region 24 is a p-type region);
a third semiconductor layer located on a portion of the second semiconductor layer (Figure 1 shows that third semiconductor layer 26 is located on a first portion of the second semiconductor layer 24 [0030]),
the third semiconductor layer contacting the second semiconductor layer (see figure 1, where third semiconductor layer 26 contacts the second semiconductor layer 24 [0030]),
and including silicon and carbon (paragraph [0017] disclose that third semiconductor layer 26 is composed of silicon carbide),
the third semiconductor layer being of the second conductivity type (paragraph [0032] discloses that third semiconductor layer 26 has p-type conductivity),
the third semiconductor layer having a higher carrier concentration than the second semiconductor layer (paragraph [0032] discloses that the p-type impurity concentration of region 26 is higher than the p-type impurity concentration of region 24);
a metal layer located on the first semiconductor layer (figure 1, 12 is a metal layer [0047]),
the metal layer forming a Schottky junction with the first semiconductor layer (see paragraph [0023]);
a second electrode located on the metal layer and connected to the metal layer (figure 1, layer 18 is an electrode located on and connected to the metal layer 12 [0050]);
and a metal film connected to the second electrode (Paragraph [0047] discloses that metal layer 12 may comprise a stacked structure of titanium and aluminum; therefore, an upper layer of the plurality of metal layers comprising layer 12, as indicated in annotated figure 1, is a metal film.),
the metal film being located in a region that is on the second electrode and includes a region directly above the third semiconductor layer (see annotated figure 1).
Regarding claim 11, Hori discloses the device according to claim 9, wherein the metal layer contacts the first, second, and third semiconductor layers (Figure 1 shows that metal layer 12 contacts semiconductor layers 20/22, 24 and 26.)
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Mizukami.
Regarding claim 2, Mizukami discloses the device according to claim 1, wherein the first semiconductor layer includes:
a first layer located on the first electrodeFigure 9 shows that first semiconductor layer 24/26 comprises a first sublayer 24, located on the first electrode 14 and a second sublayer 26, located on sublayer 24) ,
the second layer having a lower carrier concentration than the first layer (Paragraph [0052] discloses that the carrier concentration of the first layer 24 is between 1018 cm-3 and 1021 cm-3, and paragraph [0054] discloses that the carrier concentration of the second layer 216 is between 4×1014 cm.−3 and 1×1017 cm.−3; therefore, the second layer has a lower carrier concentration than the first layer)
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Mizukami lacks wherein a shortest distance between an outer edge of the fifth semiconductor layer (34a/34b) and an outer edge of the metal film (the upper metal layer of the third electrode 12, as described in the rejection of claim 1) when viewed along the first direction (Mizukami’s “third direction” in figure 3) is not less than a shortest distance between the first layer (24) and the second semiconductor layer (28/32) in the first direction (Mizukami’s “third direction” in figure 1).
However, regarding changes in size, MPEP 2144.04 IV states:
IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to make the relative dimensions of the device of claim 2 such that distance 1 (see annotated figure 3, where the indicated distance 1 is the shortest distance between an outer edge of 34a/34b and an outer edge of the metal film layer) is not shorter than distance 2 (see annotated figure 3, where the indicated distance 2 is the distance between layer 24 and the layer 28/32a/32b) in order to improve the compactness of the device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hoki.
Regarding claim 10, Hori discloses the device according to claim 9, wherein the first semiconductor layer includes:
a first layer located on the first electrode (figure 1 shows that the first layer of the first semiconductor layer 20/22 comprises layer 20); and
a second layer located on the first layer (figure 1 shows that the first semiconductor layer 20/22 has a second layer 22 located on the first layer 20),
the second layer having a lower carrier concentration than the first layer (paragraph [0020] discloses that the first layer 20 has a higher n-type impurity concentration than the second layer,)
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Hoki lacks wherein a shortest distance between an outer edge of the third semiconductor layer and an outer edge of the metal film (annotated figure 1, distance 1) when viewed along the first direction is not less than a shortest distance between the first layer and the second semiconductor layer in the first direction (annotated figure 1, distance 2).
However, regarding changes in size, MPEP 2144.04 IV states:
IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to make the relative dimensions of the device of claim 10 such that distance 1 (see annotated figure 1) is not shorter than distance 2 (see annotated figure 1) in order to improve the compactness of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Anderson et al. US 20230061775 (silicon carbide rad hard power transistors), Moon et al. US 20220336602 (SIC MOSFET device), Kurioka et al. US 20230018824 (gate insulating film in SiC MOSFET device).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 4 pm.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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