DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species 1, and Modification A1 (claims 1-6 and 8 readable thereon) in the reply filed on 12 May 2026 is acknowledged. Upon further consideration, there was not a search burden associated with the distinction of Species 1 and Species 2 as provided in the restriction requirement. Therefore, the restriction between Species 1 and Species 2 is withdrawn. Accordingly, claim 9 is rejoined. The restriction between Invention I and Invention II and the restriction between Modification A1and Modification A2 is maintained.
Drawings
The drawings are objected to because the reference character labels of FIG. 8 and FIG. 10 are illegible. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation, “the first plane is connected to the two second planes on both sides in the second direction, and the second plane is connected to the two first planes on both sides in the third direction,” in lines 3-5 of the claim. There is insufficient antecedent basis for the phrase, “the first plane,” as well as the phrase, “the second plane”. Additionally, it is unclear whether the phrase, “on both sides,” refers to the sides of second planes or the sides of first planes, in each instance of this phrase in the above quoted limitation. For the purpose of this office action, the limitation quoted above is interpreted to have the following meaning: the two first planes are connected to the two second planes.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kato et al. (US PGPub 20170012050 A1; hereinafter referred to as "Kato”).
Re claim 1: Kato teaches a semiconductor structure, comprising: a memory stack structure (FIG. 2: el. 20; para. 23-25) comprising gate line layers (FIG. 2: el. 21, 22, 23; para. 25) and gate dielectric layers (FIG. 2: el. 31; para. 25) stacked alternately in a first direction (FIG. 2: el. 21-23, 31|gate dielectric layers and gate line layers stacked alternately in the first z-direction, as labelled in FIG. 2); and isolating structures (FIG. 4A: el. 32; para. 28) and channel structures (FIG. 4A: el. 26, 36, 29; para. 28, 33, 34) that are disposed alternately in a second direction and penetrate through the memory stack structure, the second direction being perpendicular to the first direction (FIG. 4A: el. 32, (26, 36, 29); para. 22, 28|channel structures formed of channel layers 26, tunneling layers 36, and charge storage structures 29; channel structures disposed alternately with isolating structures 32 in a second x-direction; second x-direction is perpendicular with the first z-direction), wherein a channel structure of the channel structures comprises two charge storage sections disposed to be spaced from each other in a third direction (FIG. 4A: el. 29; para. 34, 60|two charge storage sections 29 disposed on either side of the channel layer and spaced apart in a third y-direction) and a common layer located between the two charge storage sections (FIG. 4A: el. 26, 36), a charge storage section of the two charge storage sections comprises a plurality of sub charge storage sections disposed to be spaced from each other in the first direction, and, in the first direction, every two adjacent sub charge storage sections of the plurality of sub charge storage sections are spaced from each other by the gate dielectric layer (FIG. 4A: el. 29; para. 34, 48, 51-52|sub-sections of the charge storage sections 29 are formed at the edge of gate lines 22 and are spaced from each other in the first z-direction by a gate dielectric layer 31), the common layer comprises a tunneling layer and a channel layer (FIG. 4A: el. 36, 26; para. 28, 33), and wherein the tunneling layer is located between the channel layer and the charge storage section (FIG. 4A: el. 36, 26, 29|tunneling layer 36 located between channel layer 26 and charge storage section 29), the third direction being perpendicular to the first direction and intersecting the second direction (para. 22).
Re claim 2: Kato teaches the semiconductor structure of claim 1, wherein the channel structure comprises two first planes opposite to each other in the second direction and two second planes opposite to each other in the third direction, the two first planes are connected to the two second planes (FIG. 4A: el. 26, 36, 29|two first planes opposite each other in the second x-direction and two second planes opposite each other in the third y-direction and the connection between the two first planes and the two second planes is shown in annotated FIG. 4A provided below).
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Re claim 3: Kato teaches the semiconductor structure of claim 2, wherein an orthogonal projection of the channel structure in the first direction has a rectangular shape (FIG. 4A: el. 26, 36, 29|rectangular shape of orthogonal projection of the channel structure in the first z-direction is apparent in annotated FIG. 4A, provided in Re claim 2 section).
Re claim 4: Kato teaches the semiconductor structure of claim 1, wherein a width of the channel structure in the third direction is larger than a width of the channel structure in the second direction (FIG. 4A: el. 26, 36, 29|width of the channel structure in the third y-direction larger than width of the channel structure in the second x-direction is apparent in annotated FIG. 4A, provided in Re claim 2 section).
Re claim 5: Kato teaches the semiconductor structure of claim 1, wherein a width of an isolating structure of the isolating structures in the third direction is smaller than a width of the channel structure in the third direction (FIG. 4A: el. 32, (26, 36, 29)|width of isolating structure 32 in third y-direction smaller than a width of the channel structure in the third direction is apparent in annotated FIG. 4A, provided in Re claim 2 section), the isolating structure faces the common layer in the second direction (FIG. 4A: el. 32, 36| isolation structure 32 faces tunneling layer 36 of the common layer), and the charge storage section and the isolating structure are staggered in the second direction (FIG. 4A: el. 32, 29).
Re claim 8: Kato teaches the semiconductor structure of claim 1, further comprising high dielectric constant layers (FIG. 4A, 4B: el. 37c; para. 36), each of which is located between the gate line layer (FIG. 4B: el. 22a) and the gate dielectric layer (FIG. 4B: el. 31) and between the gate line layer (FIG. 4A: el. 22a) and the channel structure (FIG. 4A: el. (26, 36, 29)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kato in view of Lai et al. (US 9484353 B1; hereinafter referred to as "Lai”).
Re claim 6: Kato fails to teach the semiconductor structure of claim 1, wherein the channel structure further comprises an insulating layer surrounding the two charge storage sections and the common layer.
In a similar field of endeavor, Lai teaches a semiconductor structure, comprising: a memory stack structure (FIG. 1L, 3: el. 110, 135; col. 4: line 64 – col. 5: line 12; col. 8: line 31-39) comprising gate line layers (FIG. 1L, 3: el. 135) and gate dielectric layers (FIG. 1L, 3: el. 121-127; col. 4: line 64 – col. 5: line 12) stacked alternately in a first direction (FIG. 1L); and channel structures (FIG. 1L, 3: el. 108, 107, 106; col. 7: line 30-45) that penetrate through the memory stack structure (FIG. 1L). Lai teaches a semiconductor structure, wherein the channel structure (FIG. 1L, 3: el. 108, 107, 106; col. 7: line 30-45) further comprises an insulating layer surrounding the two charge storage sections and the common layer (FIG. 1L, 3: el. 105; col. 6: line 47 – col 7: line 3). Lai further teaches a benefit of the insulating layer 105 is to increase the stability of the memory stack structure (col. 6: line 47-55).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Kato and Lai, to enable using the insulating layer surrounding a channel structure of Lai in the semiconductor structure of Kato, for the benefit of increasing the stability of the memory stack structure.
Re claim 9: The combination of Kato and Lai teaches the semiconductor structure of claim 1, wherein the common layer further comprises a supporting section surrounded by the channel layer (Lai - FIG. 1L, 3: el. 109; col. 7: line 30-45).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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