DETAILED ACTION
This Office Action is in response to an application that was filed on 12/05/2023. Claims 1-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uhlig et al. (US20210305109A1 and Uhlig hereinafter).
Regarding claim 1, Uhlig discloses a system (item 150 of Figs. 1-3 and ¶[0074] shows and indicates system 150 {electronic device 150}) comprising: a substrate (item 197 of Fig. 1 and ¶[0080] shows and indicates substrate 197 {insulating plate 197}); an electrical component mounted to the substrate (item 102 of Fig. 1 and ¶[0074] shows and indicates electrical component 102 mounted to substrate 197); a structural enclosure positioned around lateral edges of the electrical component and mounted to the substrate (items 104, 110, 112, of Fig. 1 & item 104 of Fig. 3 and ¶[0073-0074 & 0082-0082] shows and indicates structural enclosure 104 {enclosure 104 composed/formed of a soft encapsulant 110 and a rigid casing or housing 112} positioned around lateral edges of electrical component 102 and mounted to substrate 197), the structural enclosure comprising raised walls extending away from the substrate and surrounding the electrical component (item D of Fig. 1 and ¶[0073-0074 & 0082-0082] shows and indicates housing 112 of structural enclosure 104 is comprised of raised walls 104_112 {housing 112 of structural enclosure 104 that is comprised of raised walls, indicated in ¶[0082] and supported in Fig. 1} extending D distance away from substrate 197 and surrounding electrical component 102), the raised walls configured to block foreign object debris from the electrical component (item 108 of Fig. 1 and ¶[0019 & 0074] shows and indicates raised walls 104_112 with sealing 108, is configured to block foreign object debris, such as corrosive environmental gases, from electrical component 102); a lid connected to the substrate, the lid covering the electrical component and the structural enclosure (item 152 of Figs. 1-3 & items 109, 108 of Fig. 1 and ¶[0072-0075 & 0083] shows and indicates lid 152 {mounting base 152} connected to substrate 197 through housing 112 of structural enclosure 104 and seals 108 & 109; where lid 152 is covering electrical component 102 and structural enclosure 104); a seal positioned between the structural enclosure and the lid, the seal configured to be compressed when the lid is connected to the substrate (items 109, 108 of Fig. 1 and ¶[0072-0075 & 0083] shows and indicates seal 108 section of seal 108_109 is positioned between structural enclosure 104 and lid 152; where seal 108_109 is configured to be compressed when lid 152 is connected to substrate 197); and a thermal interface material positioned between and contacting the electrical component and the lid (item 110 of Fig. 1 and ¶[0042 & 0074] shows and indicates thermal interface material 110 {soft encapsulant 110, where an equilibration of thermal load may be balanced out by such a soft encapsulant, indicated in ¶[0042]} positioned between and contacting electrical component 102 and lid 152).
Regarding claim 3, Uhlig discloses a system, wherein: the electrical component comprises a semiconductor die and multiple conductive connectors electrically connecting the semiconductor die to the substrate; and the raised walls are configured to block the foreign object debris from at least the conductive connectors of the electrical component (item 198 of Fig. 1 and ¶[0037 & 0080] shows and indicates where electrical component 102 is comprised of a semiconductor die and multiple conductive connectors 198 {electrically conductive layer 198} electrically connecting the semiconductor die of electrical component 102 to substrate 197; and where raised walls 104_112 with sealing 108, are configured to block foreign object debris from conductive connectors 198 of electrical component 102).
Regarding claim 4, Uhlig discloses a system, wherein the raised walls comprise a groove configured to receive a portion of the seal (item 106 of Fig. 1 and ¶[0072-0074] shows and indicates where raised walls 104_112 is comprised groove 106 {module interface 106} configured to receive a portion of seal 108_109).
Regarding claim 6, Uhlig discloses a system, further comprising: a material at least partially filling one or more gaps between the structural enclosure and the substrate (items 108, 120 of Fig. 1 and ¶[0072-0075] shows and indicates system 150 is further comprised of material 108_120 {sealing 108 embedding the upper portion of conductive needles 120} at least partially filling one or more of the gaps between structural enclosure 104 and substrate 197).
Regarding claim 8, Uhlig discloses a system, wherein the structural enclosure remains spaced apart from the electrical component and does not contact the electrical component (Fig. 1 and ¶[0074] shows where structural enclosure 104 remains spaced apart from electrical component 102 and does not contact electrical component 102).
Claims 10, 12, 13, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uhlig.
Regarding claim 10, Uhlig discloses a method (Fig. 1 and ¶[0074] shows and indicates the method of forming Fig. 1) comprising: obtaining an electrical component mounted to a substrate (items 197, 102 of Fig. 1 and ¶[0074 & 0080] shows and indicates the method comprises obtaining electrical component 102 mounted to substrate 197 {insulating plate 197}); attaching a structural enclosure to the substrate such that the structural enclosure is positioned around lateral edges of the electrical component (items 104, 110, 112 of Fig. 1 and ¶[0073-0074 & 0082-0082] shows and indicates attaching structural enclosure 104 {enclosure 104 composed/formed of a soft encapsulant 110 and a rigid casing or housing 112} to substrate 197 such that structural enclosure 104 is positioned around lateral edges of electrical component 102), the structural enclosure comprising raised walls extending away from the substrate and surrounding the electrical component (item D of Fig. 1 and ¶[0073-0074 & 0082-0082] shows and indicates housing 112 of structural enclosure 104 is comprised of raised walls 104_112 {housing 112 of structural enclosure 104 that is comprised of raised walls, indicated in ¶[0082] and supported in Fig.1} extending D distance away from substrate 197 and surrounding electrical component 102), the raised walls configured to block foreign object debris from the electrical component (item 108 of Fig. 1 and ¶[0019 & 0074] shows and indicates raised walls 104_112 with sealing 108, is configured to block foreign object debris, such as corrosive environmental gases, from electrical component 102); placing a thermal interface material over the electrical component (item 110 of Fig. 1 and ¶[0042 & 0074] shows and indicates placing thermal interface material 110 {soft encapsulant 110, where an equilibration of thermal load may be balanced out by such a soft encapsulant, indicated in ¶[0042]} over electrical component 102); placing a seal over the structural enclosure (items 109, 108 of Fig. 1 and ¶[0072-0075 & 0083] shows and indicates placing seal 108 section of seal 108_109 over structural enclosure 104); and connecting a lid to the substrate, the lid covering the electrical component and the structural enclosure (items 152, 109, 108 of Fig. 1 and ¶[0072-0075 & 0083] shows and indicates connecting lid 152 {mounting base 152} to substrate 197 through housing 112 of structural enclosure 104 and seals 108 & 109; where lid 152 is covering electrical component 102 and structural enclosure 104), the seal being compressed when the lid is connected to the substrate (Fig. 1 and ¶[0072-0075 & 0083] shows and indicates seal 108_109 is compressed when lid 152 is connected to substrate 197).
Regarding claim 12, Uhlig discloses a method, wherein: the electrical component comprises a semiconductor die and multiple conductive connectors electrically connecting the semiconductor die to the substrate; and the raised walls are configured to block the foreign object debris from at least the conductive connectors of the electrical component (item 198 of Fig. 1 and ¶[0037 & 0080] shows and indicates a method of forming Fig. 1 where electrical component 102 is comprised of a semiconductor die and multiple conductive connectors 198 {electrically conductive layer 198} electrically connecting the semiconductor die of electrical component 102 to substrate 197; and where raised walls 104_112 with sealing 108, are configured to block foreign object debris from conductive connectors 198 of electrical component 102).
Regarding claim 13, Uhlig discloses a method, wherein the raised walls comprise a groove configured to receive a portion of the seal (item 106 of Fig. 1 and ¶[0072-0074] shows and indicates a method of forming Fig. 1 where raised walls 104_112 is comprised groove 106 {module interface 106} configured to receive a portion of seal 108_109).
Regarding claim 15, Uhlig discloses a method, further comprising: a material at least partially filling one or more gaps between the structural enclosure and the substrate (items 108, 120 of Fig. 1 and ¶[0072-0075] shows and indicates a method of forming Fig. 1 is further comprised of material 108_120 {sealing 108 embedding the upper portion of conductive needles 120} at least partially filling one or more of the gaps between structural enclosure 104 and substrate 197).
Regarding claim 17, Uhlig discloses a method, wherein the structural enclosure remains spaced apart from the electrical component and does not contact the electrical component (Fig. 1 and ¶[0074] shows a method of forming Fig. 1 where structural enclosure 104 remains spaced apart from electrical component 102 and does not contact electrical component 102).
Claims 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uhlig.
Regarding claim 19, Uhlig discloses an apparatus (item 150 of Figs. 1-3 and ¶[0074] shows and indicates apparatus 150 {electronic device 150}) comprising: a structural enclosure configured to be mounted to a substrate and positioned around lateral edges of an electrical component mounted to the substrate (items 104, 110, 112, 197, 102 of Fig. 1 & item 104 of Fig. 3 and ¶[0073-0074_0080 & 0082-0082] shows and indicates structural enclosure 104 {enclosure 104 composed/formed of a soft encapsulant 110 and a rigid casing or housing 112} configured to be mounted to substrate 197 {insulating plate 197} and positioned around lateral edges of electrical component 102 mounted to substrate 197); wherein the structural enclosure comprises raised walls configured to surround the electrical component (Fig. 1 and ¶[0073-0074 & 0082-0082] shows and indicates housing 112 of structural enclosure 104 is comprised of raised walls 104_112 {housing 112 of structural enclosure 104 that is comprised of raised walls, indicated in ¶[0082] and supported in Fig. 1} configured to surround electrical component 102), the raised walls configured to block foreign object debris from the electrical component (item 108 of Fig. 1 and ¶[0019 & 0074] shows and indicates raised walls 104_112 with sealing 108, is configured to block foreign object debris, such as corrosive environmental gases, from electrical component 102); and wherein the raised walls comprise or are configured to cooperate with a groove configured to receive a portion of a seal (item 106 of Fig. 1 and ¶[0072-0074] shows and indicates where raised walls 104_112 is comprised and configured to cooperate with groove 106 {module interface 106} that is configured to receive a portion of seal 108_109).
Regarding claim 20, Uhlig discloses an apparatus, wherein the structural enclosure is configured to retain at least some of a thermal interface material in a space between the electrical component and a lid positioned over the structural enclosure and the electrical component (items 110, 152 of Fig. 1 & item 152 of Figs. 2-3 and ¶[0042_0072-0075 & 0083] shows and indicates where the lower portion of structural enclosure 104 will be configured to retain some of thermal interface material 110 {soft encapsulant 110, where an equilibration of thermal load may be balanced out by such a soft encapsulant, indicated in ¶[0042]} in a space between electrical component 102 and lid 152 {mounting base 152}; and where lid 152 is positioned over structural enclosure 104 and electrical component 102).
Allowable Subject Matter
Claims 2, 5, 7, 9, 11, 14, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the primary reason for allowance is due to a system, wherein the structural enclosure, the lid, and the seal are configured to retain at least some of the thermal interface material in a space between the electrical component and the lid.
Regarding claim 5, the primary reason for allowance is due to a system, wherein each of the raised walls has a non-uniform thickness such that an upper portion of each raised wall is thicker than a lower portion of the raised wall.
Regarding claim 7, the primary reason for allowance is due to a system, wherein the structural enclosure comprises a three-dimensional (3D) printed structure.
Regarding claim 9, the primary reason for allowance is due to a system, wherein: the electrical component comprises a semiconductor die and a ball grid array; the substrate comprises a printed circuit board; the ball grid array is surface-mounted to a surface of the printed circuit board; and the structural enclosure is attached to the surface of the printed circuit board.
Regarding claim 11, the primary reason for allowance is due to a method, wherein the structural enclosure, the lid, and the seal retain at least some of the thermal interface material in a space between the electrical component and the lid.
Regarding claim 14, the primary reason for allowance is due to a method, wherein each of the raised walls has a non-uniform thickness such that an upper portion of each raised wall is thicker than a lower portion of the raised wall.
Regarding claim 16, the primary reason for allowance is due to a method, wherein the structural enclosure comprises a three-dimensional (3D) printed structure.
Regarding claim 18, the primary reason for allowance is due to a method, wherein: the electrical component comprises a semiconductor die and a ball grid array; the substrate comprises a printed circuit board; the ball grid array is surface-mounted to a surface of the printed circuit board; and the structural enclosure is attached to the surface of the printed circuit board.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847