Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-7, 11-13 and 16-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. (US Pub. No. 2024/0071987 A1), hereafter referred to as Hsu.
As to claim 1, Hsu discloses a semiconductor device (fig 2, [0025]), comprising:
a first die (fig 2, 201) comprising a first bonding layer (120/225) and
a first metal ring (210; [0027]), wherein the first bonding layer (120/225) includes a first connection structure (225a) and the first metal ring (210) is disposed around the first connection structure (fig 3, 210 is around 225).
As to claim 2, Hsu discloses the semiconductor device of claim 1 (paragraphs above),
wherein the first metal ring is closed around the first connection structure (fig 3, 210 in closed ring around 225).
As to claim 6, Hsu discloses the semiconductor device of claim 1 (paragraphs above),
a second die (fig 2, 201b) corresponding to the first die (201a), the second die including a second bonding layer (120/225),
wherein the second bonding layer includes a second connection structure (225) and a second metal ring (210) disposed around the second connection structure (225).
As to claim 7, Hsu discloses the semiconductor device of claim 6 (paragraphs above),
wherein the second metal ring (210) is closed around the second connection structure (225) and an orthographic projection of the first metal ring on the second die at least partially overlaps with the second metal ring (fig 2, 210).
As to claim 11, Hsu discloses a fabrication method of a semiconductor device (fig 2, [0025]), comprising:
providing a first die (201a) and a second die (201b), wherein the first die comprises a first bonding layer (120), a first connection structure (225) and a first metal ring (210), the first metal ring closed around the first connection structure (fig 3, 300B), the second die (201b) including a second bonding layer (120) and a second connection structure (225);
disposing the first bonding layer and the second bonding layer in face-to-face manner (fig 2, 200B), the first connection structure and the second connection structure being disposed in a contraposition contact manner (fig 2, 200B); and
connecting the first connection structure with the second connection structure by bonding ([0028]).
As to claim 12, Hsu discloses the fabrication method of the semiconductor device of claim 11 (paragraphs above),
wherein in providing the first die and the second die, the first connection structure is exposed to a surface of the first bonding layer (fig 2, 225 exposed by 120), the first metal ring is exposed to the surfaces of the first bonding layer ([0028]), the second connection structure is exposed to a surface of the second bonding layer (fig 2, 225 exposed by 120).
As to claim 13, Hsu discloses the fabrication method of the semiconductor device of claim 11 (paragraphs above),
wherein connecting the first connection structure with the second connection structure by bonding comprises:
disposing an electromagnetic induction heater at peripheries of the first bonding layer and the second bonding layer ([0029]); and
starting the electromagnetic induction heater to connect the first connection structure with the second connection structure by bonding ([0029]).
As to claim 16, Hsu discloses the fabrication method of the semiconductor device of claim 11 (paragraphs above),
wherein providing the first die and the second die comprises:
providing a first wafer comprising a plurality of the first die ([0022]),
wherein a plurality of the first metal ring are disposed around the plurality of the first die (plurality of ring 210; [0022]); and
wherein providing the first wafer comprises:
providing a first dielectric layer (120), the first dielectric layer connecting a plurality the first bonding layer (225) of the plurality of the first die (201a),
wherein the plurality of the first metal ring (210) are disposed in the first dielectric layer (120) and the plurality of the first bonding layer (225).
As to claim 17, Hsu discloses the fabrication method of the semiconductor device of claim 11 (paragraphs above),
wherein in providing the plurality of the first die and a plurality of the second die, the plurality of the second die further comprise second metal rings (210) that are exposed to surfaces of the plurality of the second bonding layer ([0028]), each of the second metal rings is disposed as being closed around at least one of a plurality of the second connection structure (225).
As to claim 18, Hsu discloses the fabrication method of the semiconductor device of claim 17 (paragraphs above),
wherein providing the first die and the second die comprises:
providing a second wafer comprising a plurality of the second die ([0022]),
wherein a plurality of the second metal ring are disposed around the plurality of the second die (plurality of ring 210; [0022]); and
wherein providing the second wafer comprises:
providing a second dielectric layer (120), the second dielectric layer connecting a plurality of the second bonding layer (225) of the plurality of the second die,
wherein a plurality of the second metal ring (210) are disposed in the second dielectric layer (120) and the plurality of the second bonding layer (225).
As to claim 19, Hsu discloses the fabrication method of the semiconductor device of claim 17 (paragraphs above),
wherein in disposing the first bonding layer and the second bonding layer in face-to-face manner (fig 2, [0028]), with the first connection structure and the second connection structure being disposed in a contraposition contact manner (225), an orthographic projection of the first metal ring on the second die at least partially overlaps with the second metal ring (fig 2, rings 210).
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Eid et al. (US Pub. No. 2021/0375820 A1), hereafter referred to as Eid.
As to claim 20, Eid discloses a semiconductor apparatus (fig 3, [0041]), comprising:
an electromagnetic induction heater (180) configured to surround a semiconductor device in a bonding process ([0041]); and
a first die (110; [0023]) including a first bonding layer (118), wherein a first metal ring (150; [0038]) is disposed around a first connection structure (130).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Totani et al. (US Pub. No. 2023/0361061 A1), hereafter referred to as Totani.
As to claim 3, Hsu discloses the semiconductor device of claim 1 (paragraphs above),
wherein the first die (201) includes a first substrate (110), a first circuit layer ([0020]) located on the first substrate (110), and the first bonding layer (120) located on the first circuit layer ([0020]).
Hsu does not disclose the first connection structure includes a first connection line and a first connection terminal, the first connection line is connected with the first circuit layer, the first connection terminal is disposed at an end of the first connection line far away from the first circuit layer.
Nonetheless, Totani discloses a first connection structure (fig 3A, 28) includes a first connection line (760) and a first connection terminal (26), the first connection line (760) is connected with a first circuit layer (700), the first connection terminal (26) is disposed at an end of the first connection line (760) far away from the first circuit layer (700).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include connection terminal and connection line to a circuit layer in the device of Hsu as taught by Totani since this will allow for the electrical interconnection of circuits from the die output from the semiconductor device.
As to claim 4, Hsu in view of Totani disclose the semiconductor device of claim 3 (paragraphs above).
Hsu does not explicitly disclose wherein in a direction perpendicular to the first bonding layer, a thickness of the first metal ring is 1-3 times of a thickness of the first connection terminal.
Nonetheless, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness of the metal ring within the range of 1-3 times the thickness of the first connection terminal since Hsu shows in figure 2 that the metal ring is approximately one times the thickness of the first connection terminal and one of ordinary skill in the art would have recognized that the heating of the terminal would be optimized by controlling the thickness of the ring that is used by being energized to transfer thermal energy to the terminal of equal thickness such that the heat transfer regions are adjacently located.
As to claim 8, Hsu discloses the semiconductor device of claim 6 (paragraphs above),
wherein the second die (201b) includes a second substrate (110), a second circuit layer located on a side of the second substrate close to the first die ([0020]), and the second bonding layer (120) is located on a side of the second circuit layer close to the first die ([0020]).
Hsu does not disclose the second connection structure includes a second connection line and a second connection terminal, the second connection line is connected with the second circuit layer, the second connection terminal is disposed at an end of the second connection line far away from the second circuit layer.
Nonetheless, Totani discloses a second connection structure (fig 3A, 18) includes a second connection line (960) and a second connection terminal (16), the second connection line (960) is connected with a second circuit layer (900), the second connection terminal (16) is disposed at an end of the second connection line (960) far away from the second circuit layer (900).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include connection terminal and connection line to a circuit layer in the device of Hsu as taught by Totani since this will allow for the electrical interconnection of circuits from the die output from the semiconductor device.
As to claim 9, Hsu in view of Totani disclose the semiconductor device of claim 8 (paragraphs above).
Hsu does not explicitly disclose wherein a thickness of the second metal ring is 1-3 times of a thickness of the second connection terminal.
Nonetheless, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness of the metal ring within the range of 1-3 times the thickness of the first connection terminal since Hsu shows in figure 2 that the metal ring is approximately one times the thickness of the first connection terminal and one of ordinary skill in the art would have recognized that the heating of the terminal would be optimized by controlling the thickness of the ring that is used by being energized to transfer thermal energy to the terminal of equal thickness such that the heat transfer regions are adjacently located.
Claim(s) 5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Totani and further in view of Ayotte et al. (US Pub. No. 2015/0294948 A1), hereafter referred to as Ayotte.
As to claim 5, Hsu in view of Totani disclose the semiconductor device of claim 3 (paragraphs above).
Hsu does not disclose wherein the first connection structure further includes a first heat preservation portion that is disposed on a sidewall of the first connection terminal.
Nonetheless, Ayotte discloses a similar connection structure thermal bonding heat preservation portion and induction heating ring (fig 7, 136 and 118 with connection structure 128).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further include the heat perseveration portion in the device of Hsu in view of Totani as taught by Ayotte since this will improve the efficiency of heating the contact structure.
As to claim 10, Hsu in view of Totani disclose the semiconductor device of claim 8 (paragraphs above).
Hsu does not disclose wherein the second connection structure further includes a second heat preservation portion that is disposed on a sidewall of the second connection terminal.
Nonetheless, Ayotte discloses a similar connection structure thermal bonding heat preservation portion and induction heating ring (fig 7, 136 and 118 with connection structure 128).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further include the heat perseveration portion in the device of Hsu in view of Totani as taught by Ayotte since this will improve the efficiency of heating the contact structure.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Hsiao et al. (US Pub. No. 2021/0050251 A1), hereafter referred to as Hsiao.
As to claim 14, Hsu discloses the fabrication method of the semiconductor device of claim 13 (paragraphs above),
Hsu does not disclose wherein the electromagnetic induction heater comprises a coil assembly, alternating current is set within coils in the coil assembly, the coil assembly generates magnetic field perpendicular to the first bonding layer.
Nonetheless, Hsiao discloses wherein an electromagnetic induction heater comprises a coil assembly, alternating current is set within coils in the coil assembly, the coil assembly generates magnetic field perpendicular to a first bonding layer (fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to use the coils of the induction heater of Hsiao as the induction heater of Hsu since this will provide uniform heat control for the bonding process.
As to claim 15, Hsu in view of Hsiao disclose the fabrication method of the semiconductor device of claim 14 (paragraphs above),
Hsiao further discloses wherein the coil assembly comprises a first winding area and second winding areas located on two sides of the first winding area (fig 5, winding areas 112’),
wherein the first winding area corresponds to the first bonding layer, a coil density within the first winding area is greater than a coil density within the second winding areas (fig 5, winding area to the left and right of the bonding layer has more densely arranged wirings).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2009/0188704 A1; and US Patent No. 9,190,375 B2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 1/30/2026