DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 7, 14, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter.
Claims 3-4, 6, 10-11, 13, and 17-18 are rejected under 35 U.S.C. 101.
As per claim 3, the claim recites an integrated circuits, therefore is a manufacture.
“ . . . determine a performance level … “ These limitations, as drafted, are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
The limitation of “receive a request . . . ”, amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
As discussed above, “receive a request . . . ”, amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). “service the request . . . service the request . . . a plurality of semiconductor dies, wherein the second functional block and the third functional block are located on different semiconductor dies of the plurality of semiconductor dies . . . ” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Bass/ChoFleming. The claim is ineligible.
As per claim 4, the claim recites an integrated circuits, therefore is a manufacture.
“ . . . determine a performance level … “ These limitations, as drafted, are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
The limitation of “receive a request . . . ”, amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
As discussed above, “receive a request . . . ”, amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). “service the request . . . service the request . . . a plurality of semiconductor dies, wherein the second functional block and the third functional block are located on different semiconductor dies of the plurality of semiconductor dies . . . ” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Bass/ChoFleming. The claim is ineligible.
As per claim 6, see rejection on claim 4. “generate a mapping . . . “ These limitations, as drafted, are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
“convey . . . “ amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
As per claim 10, see rejection on claim 3.
As per claim 11, see rejection on claim 4.
As per claim 13, see rejection on claim 6.
As per claim 17, see rejection on claim 3.
As per claim 18, see rejection on claim 4.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 8, 11, 15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bass et al (US 2013/0152099) (hereinafter Bass) .
As per claim 1, Bass teaches:
An integrated circuit comprising:
circuitry configured to:
receive a request (Bass, [0025]);
service the request using a first functional block and a second functional block, responsive to the request requiring a first performance level (Bass, [0024], [0025]—under BRI, a first functional block and a second functional block can be blocks from 705, 706 + DMA; under BRI, a first performance level can be performance level relating to AES-SHA); and
service the request using the first functional block and a third functional block different from the second functional block, responsive to the request requiring a second performance level different from the first performance level (Bass, [0024], [0025]—under BRI, a 3rd functional block different from the second functional block can be AMF 707; under BRI, a second performance level different from the first performance level can be level relating to AMF functions).
As per claim 4, Bass teaches:
The integrated circuit as recited in claim 2 (see rejection on claim 2), wherein the circuitry is further configured to determine a performance level of one or more functional blocks based on identifiers of the functional blocks (Bass, [0024],[0025]).
As per claim 8, see rejection on claim 1.
As per claim 11, see rejection on claim 4.
As per claim 15, see rejection on claim 1.
As per claim 18, see rejection on claim 4.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5, 9-10, 12, 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bass et al in view of ChoFleming et al ( US 2023/0367640) (hereinafter ChoFleming).
As per claim 2, Bass teaches:
The integrated circuit as recited in claim 1 (see rejection on claim 1).
Bass does not expressly teach:
further comprising a plurality of semiconductor dies, wherein the second functional block and the third functional block are located on different semiconductor dies of the plurality of semiconductor dies.
However, ChoFleming discloses:
further comprising a plurality of semiconductor dies, wherein the second functional block and the third functional block are located on different semiconductor dies of the plurality of semiconductor dies (ChoFelming, [0093]).
Both ChoFleming and Bass pertain to the art of integrated circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use ChoFleming’s method to use multiple dies because it is well-known in the art that multi-die packaging (chiplets/System-in-Package) enhances semiconductor design by increasing yield, reducing costs, and enabling heterogeneous integration.
As per claim 3, Bass teaches:
The integrated circuit as recited in claim 2 (See rejection on claim 2), wherein the circuitry is further configured to determine a performance level of the request based on endpoint features specified in the request (Bass, [0025]—under BRI, endpoint features can be the type of co-processor operation).
As per claim 5, Bass teaches:
The integrated circuit as recited in claim 4 (see rejection on claim 4).
Bass does not expressly teach:
wherein one or more semiconductor dies of the plurality of semiconductor dies provide a different performance level than other semiconductor dies of the plurality of semiconductor dies.
However, ChoFleming discloses:
wherein one or more semiconductor dies of the plurality of semiconductor dies provide a different performance level than other semiconductor dies of the plurality of semiconductor dies (ChoFleming, Fig 8, core 808, cache 814).
Both ChoFleming and Bass pertain to the art of integrated circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use ChoFleming’s method to use multiple dies having different level of providing functions because multi-die packaging (chiplets/System-in-Package) enhances semiconductor design by increasing yield, reducing costs, and enabling heterogeneous integration.
As per claim 9, see rejection on claim 2.
As per claim 10, see rejection on claim 3.
As per claim 12, see rejection on claim 5.
As per claim 16, see rejection on claim 2.
As per claim 17, see rejection on claim 3.
As per claim 19, see rejection on claim 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 8869160 teaches a method of using accelerators to provide different performance levels.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLIE SUN/Primary Examiner, Art Unit 2198
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