DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/12/2026 have been fully considered but they are not persuasive.
On page 10 of the remark, applicant argued: “Likewise, dispatching a job to an accelerator engine is not the same as causing an integrated-circuit interconnect to provide the claimed communication paths. Bass describes queue- based dispatching of jobs to hardware accelerators. In contrast, amended claim 1 recites circuitry that causes an interconnect to provide different communication paths for data associated with a request between the same first functional block and either a second functional block or a third functional block, depending on information associated with the request indicating different performance levels.” Applicant’s arguments focus on new claim amendments. See new ground of rejection.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter.
Claims 6 and 13 are rejected under 35 U.S.C. 101.
ineligible.
As per claim 6, see rejection on claim 1. “generate a mapping . . . “ These limitations, as drafted, are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
“convey . . . “ amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
As per claim 13, see rejection on claim 6.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 8, 10, 15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bass et al (US 2013/0152099) (hereinafter Bass) .
As per claim 1, Bass teaches:
An integrated circuit comprising:
circuitry configured to:
receive a request (Bass, [0025]);
cause an interconnect of the integrated circuit to route data associated with the request between a first functional block of the integrated circuit and a second functional block of the integrated circuits (Bass, [0024], [0025]—data is routed from 705, 706 + DMA to AES), responsive to information associated with the request indicating a first performance level (Bass, [0024, 0025); and
cause the interconnect to route data associated with the request between the first functional block and a third functional block of the integrated circuit (Bass, [0024], [0025]—data is routed between DMA and AMF) , responsive to information associated with the request indicating a second performance level different from the first performance level (Bass, [0024], [0025]), responsive to information associated with the request(Bass, [0024], [0025]).
As per claim 3, Bass teaches:
The integrated circuit as recited in claim 1 (see rejection on claim 1), wherein the performance level of the request is based at least in part on endpoint features specified in the request (Bass, [0025]).
As per claim 8, see rejection on claim 1.
As per claim 10, see rejection on claim 3.
As per claim 15, see rejection on claim 1.
As per claim 17, see rejection on claim 3.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bass et al in view of ChoFleming et al ( US 2023/0367640) (hereinafter ChoFleming).
As per claim 2, Bass teaches:
The integrated circuit as recited in claim 1 (see rejection on claim 1).
Bass does not expressly teach:
further comprising a plurality of semiconductor dies, wherein the second functional block and the third functional block are located on different semiconductor dies of the plurality of semiconductor dies.
However, ChoFleming discloses:
further comprising a plurality of semiconductor dies, wherein the second functional block and the third functional block are located on different semiconductor dies of the plurality of semiconductor dies (ChoFelming, [0093]).
Both ChoFleming and Bass pertain to the art of integrated circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use ChoFleming’s method to use multiple dies because it is well-known in the art that multi-die packaging (chiplets/System-in-Package) enhances semiconductor design by increasing yield, reducing costs, and enabling heterogeneous integration.
As per claim 9, see rejection on claim 2.
As per claim 16, see rejection on claim 2.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bass in view of Zeng et al (US 2019/0146842) (hereinafter Zeng).
As per claim 4, Bass teaches:
The integrated circuit as recited in claim 1 (see rejection on claim 1).
Bass does not expressly teach:
wherein the integrated circuit comprises stored information associated with one or more of the second functional block or the third functional block, and wherein the stored information indicates one or more of a performance bin, a maximum operating clock frequency, or voltage-frequency scaling data;
However, Zeng discloses:
wherein the integrated circuit comprises stored information associated with one or more of the second functional block or the third functional block (Zeng, [0029]), and wherein the stored information indicates one or more of a performance bin, a maximum operating clock frequency, or voltage-frequency scaling data (Zeng, [0029]);
Both Zeng and Bass pertain to the art of integrated circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Zeng’s method to stored performance information because it is well-known in the art that performance information is an important decision variable associated with selection of functional blocks
As per claim 11, see rejection on claim 4.
As per claim 18, see rejection on claim 4.
Claims 5, 12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bass in view of Narvaez et al (US 2014/0189704) (hereinafter Narvaez).
As per claim 5, Bass teaches:
The integrated circuit as recited in claim 1 (see rejection on claim 1).
Bass does not expressly teach:
wherein each of the second functional block and the third functional block comprise circuitry configured to perform a same function.
However, Narvaez discloses:
wherein each of the second functional block and the third functional block comprise circuitry configured to perform a same function (Narvaez, [0095]—under BRI, performing same function can be performing threads).
Both Narvaez and Bass pertain to the art of integrated circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Narvaez’s method to use multiple cores performing same function because it is well-known in the art that independent processing units on a single chip that can execute tasks in parallel, thus improving performance and throughput.
As per claim 12, see rejection on claim 5.
As per claim 19, see rejection on claim 5
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bass in view of Watanabe et al (US 8881200) (hereinafter Watanabe).
As per claim 7, Bass teaches:
The integrated circuit as recited in claim 1 (see rejection on claim 1).
Bass does not expressly teach:
the second functional block and the third functional block are instantiated copies of a frontend circuit that processes rendered video data; and the first functional block is a backend circuit that processes data generated by the frontend circuit.
However, Watanabe discloses: the second functional block and the third functional block are instantiated copies of a frontend circuit that processes rendered video data (Watanabe, col 8, ll 15-17); and the first functional block is a backend circuit that processes data generated by the frontend circuit (Watanabe, col 8 ll 22-25).
Both Watanabe and Bass pertain to the art of integrated circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Watanabe’s method to use decode and scale video because it is well-known in the art that video decoders and scalers are essential processing tools. Decoders decompress streaming data into viewable formats, while scalers adjust resolution to fit screens properly. Together, they optimize bandwidth, guarantee display compatibility, and prevent buffering for a flawless viewing experience across all devices
As per claim 20, see rejection on claim 7.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Bass applied to claim 8 above, and further in view of Mital et al (US 2023/0118325) (hereinafter Mital) .
As per claim 14, Bass teaches:
The method as recited in claim 8 (see rejection on claim 8).
Bass does not expressly teach:
each of the second functional block and the third functional block is an are instantiated copies of same circuitry.
However, Mital discloses:
each of the second functional block and the third functional block is an are instantiated copies of same circuitry (Mital, [0029]).
Both Mital and Bass pertain to the art of integrated circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Mital’s method to instantiate same circuits because it is well-known in the art that instantiable circuits provide a structured method to isolate electrical power, allowing specific high-draw appliances or sensitive equipment to operate independently. This modularity prevents systemic overloads, mitigates fire hazards, and guarantees each device receives its required power rating for optimal performance
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLIE SUN/Primary Examiner, Art Unit 2198
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