Prosecution Insights
Last updated: April 19, 2026
Application No. 18/530,272

Integrated transformer

Non-Final OA §103
Filed
Dec 06, 2023
Examiner
TRAN, TONY
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Real Tek Semiconductor Corporation
OA Round
3 (Non-Final)
70%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allow Rate
597 granted / 850 resolved
+2.2% vs TC avg
Strong +34% interview lift
Without
With
+34.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
61 currently pending
Career history
911
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
59.0%
+19.0% vs TC avg
§102
35.2%
-4.8% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 850 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/19/2025 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over YEN (Pub. No.: US 2017/0098500). PNG media_image1.png 670 1032 media_image1.png Greyscale PNG media_image2.png 552 779 media_image2.png Greyscale Re claim 1, YEN, FIG. 3B [as shown above] teaches an integrated transformer comprising: a first inductor (310), substantially implemented in a first metal layer [FM] of a semiconductor structure and comprising a first winding and a second winding, wherein the first winding has a first end point (313) and a second end point [SEP], the second winding has a third end point [TEP] and a fourth end point [FEP], the first end point is connected to the third end point through a first segment [FS], and the second end point [SEP] is connected to the fourth end point [FEP] through a second segment [SS]; and a second inductor (320), substantially implemented in a second metal layer [SM] of the semiconductor structure and comprising a third winding and a fourth winding, wherein the third winding has a fifth end point [FEP] and a sixth end point [SIXEP], the fourth winding has a seventh end point (323) and an eighth end point [EEP], the fifth end point is connected to the seventh end point through a third segment [TS], and the sixth end point [SixEP] is connected to the eighth end point through a fourth segment [FourS]; and wherein the first segment [FS] and the second segment [SS] form a first crossing structure, the third segment [TS] and the fourth segment [FourS] form a second crossing structure, the first segment [FS] and the third segment [TS] are implemented in the first metal layer [FM], the second segment [SS] and the fourth segment [FourS] are implemented in the second metal layer [SM], and the first metal layer [FM] is different from the second metal layer [SM]. Re claim 2, YEN, FIG. 3B [as shown above] teaches the integrated transformer of claim 1, wherein the first winding comprises a fifth segment (330) using the first end point as one end point, and the third winding comprises a sixth segment (340) using the fifth end point as one end point, a portion of the fifth segment and a portion of the sixth segment substantially overlap. Re claim 3, YEN, FIG. 3B [as shown above] teaches the integrated transformer of claim 2, wherein the first winding and the third winding substantially overlap (thru 330), and the second winding and the fourth winding substantially overlap (thru 340). Re claim 4, YEN, FIG. 3B [as shown above] teaches the integrated transformer of claim 2, wherein the first inductor and the second inductor substantially overlap (330/340). Re claim 5, YEN, FIG. 3B [as shown above] teaches the integrated transformer of claim 1, wherein the first winding has a first inner turn and a first outer turn, a first output/input terminal (311a) and a second output/input terminal (312a) of the first inductor are located at the first outer turn, the fourth winding has a second inner turn and a second outer turn, and a third output/input terminal (bottom 321) and a fourth output/input terminal (top 321) of the second inductor are located at the second outer turn. Re claim 6, YEN, FIG. 3B [as shown above] teaches the integrated transformer of claim 1, wherein the first winding has a first inner turn and a first outer turn, a first output/input terminal (311a) and a second output/input terminal (312a) of the first inductor are located at the first outer turn (311/312), the fourth winding has a second inner turn and a second outer turn, and a third output/input terminal (bottom 312) and a fourth output/input terminal (top 321) of the second inductor are located at the second inner turn. Re claim 7, YEN, FIG. 3B [as shown above] teaches the integrated transformer of claim 1, wherein the first winding has a first inner turn and a first outer turn, a first output/input terminal and a second output/input terminal of the first inductor are located at the first inner turn (by 330), the fourth winding has a second inner turn and a second outer turn, and a third output/input terminal and a fourth output/input terminal of the second inductor are located at the second inner turn (by 340). Re claim 8, YEN, FIG. 3B [as shown above] teaches the integrated transformer of claim 1, wherein at least one segment (330) of the first inductor (310) is implemented in the second metal layer, at least one segment (340) of the second inductor (320) is implemented in the first metal layer, and the integrated transformer uses only two metal layers. Re claim 9, YEN, FIG. 3B [as shown above] teaches the integrated transformer of claim 8, wherein the first winding has a first outer turn (by [FS]), the second winding has a second outer turn (by TS], the third winding has a third outer turn (by FourS], the fourth winding has a fourth outer turn (by [SS]), the at least one segment of the first inductor is arranged within the third outer turn and the fourth outer turn, and the at least one segment of the second inductor is arranged within the first outer turn and the second outer turn. OR IT COULD BE REJECTED AS: PNG media_image3.png 200 400 media_image3.png Greyscale Re claim 1, YEN, Fig. 3B [as shown above] teaches an integrated transformer comprising: a first inductor (310), substantially implemented in a first metal layer (315b+340) of a semiconductor structure and comprising a first winding and a second winding, wherein the first winding has a first end point and a second end point, the second winding has a third end point and a fourth end point, the first end point is connected (electrically) to the third end point through a first segment [FS], and the second end point is connected (electrically) to the fourth end point through a second segment [SS]; and a second inductor (320), substantially implemented in a second metal layer (325a+380) of the semiconductor structure and comprising a third winding and a fourth winding, wherein the third winding has a fifth end point and a sixth end point, the fourth winding has a seventh end point and an eighth end point, the fifth end point is connected (electrically) to the seventh end point through a third segment, and the sixth end point is connected (electrically) to the eighth end point through a fourth segment; and wherein the first segment [FS] and the second segment [SS] form a first crossing structure, the third segment [TS] and the fourth segment [FourS] form a second crossing structure, the first segment [FS] and the third segment [TS] are implemented in the first metal layer [315b+340], the second segment [SS] and the fourth segment [FourS] are implemented in the second metal layer (325a+380), and the first metal layer (315b+340) is different from the second metal layer (325a+380). Allowable Subject Matter Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: In the claim 10 that is written, the prior arts fail to show or fairly suggest “wherein the first segment and the third segment are not implemented in the second metal layer, and the second segment and the fourth segment are not implemented in the first metal layer” in context with the other limitation as stated in claim 1. Response to Arguments Applicant's arguments filed 12/19/2025 have been fully considered but they moot due to a new ground of rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONY TRAN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Dec 06, 2023
Application Filed
Apr 24, 2025
Non-Final Rejection — §103
Jul 21, 2025
Response Filed
Sep 22, 2025
Final Rejection — §103
Dec 19, 2025
Request for Continued Examination
Jan 12, 2026
Response after Non-Final Action
Feb 06, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604527
DISPLAY PANEL AND DISPLAY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12598731
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
2y 5m to grant Granted Apr 07, 2026
Patent 12593677
SEMICONDUCTOR DEVICE STRUCTURE WITH ENERGY REMOVABLE STRUCTURE AND METHOD FOR PREPARING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12588395
Display Substrate and Preparation Method thereof, and Display Apparatus
2y 5m to grant Granted Mar 24, 2026
Patent 12588288
ACTIVE DEVICE SUBSTRATE
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
70%
Grant Probability
99%
With Interview (+34.0%)
2y 11m
Median Time to Grant
High
PTA Risk
Based on 850 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month