DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 12/06/2023 and 08/13/2024 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by, or alternatively under 35 U.S.C. 103 as obvious over Chonghua Zhong et al, (hereinafter ZHONG), US 20200273843 A1.
Regarding Claim 1, ZHONG teaches a structure (Fig. 1, 300, PoP structure), comprising:
an integrated circuit (IC) die (Fig. 1, 140, first die)
an interposer die (Fig. 1, 130, vertical interposer) electrically connected (Fig. 4E, 171, routing to electrically connect the vertical interposer, 130 and first die, 140, [0033]) to the IC die (Fig. 1, 140, first die);
a first bonding structure (annotated Figure 1) disposed on the IC die (Fig. 1, 140, first die);
a second bonding structure (annotated Figure 1) bonded to the first bonding structure (annotated Figure 1);
a molding compound layer (Figs. 1/4F, 150) disposed on the second bonding structure (annotated Figure 1); and
a frame structure (Figs. 1/4C, 104, conductive pillars) disposed on the second bonding structure (annotated Figure 1); and surrounding the IC die (Fig. 1, 140, first die).
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Regarding Claim 2, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, wherein the frame structure (Figs. 1/4C, 104, conductive pillars) surrounds the first bonding structure (annotated Figure 1).
Regarding Claim 3, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, wherein the frame structure (Figs. 1/4C, 104, conductive pillars, [0031]) is disposed in the molding compound layer (Figs. 1/4F, 150, [0031]).
Regarding Claim 4, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, wherein the frame structure (Figs. 1/4C, 104, conductive pillars) comprises (the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) a thermal expansion coefficient lower (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) than a thermal expansion coefficient (according to TopLine QFN CTE of molding compound, 30x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the molding compound layer (Figs. 1/4F, 150, [0031]).
Regarding Claim 5, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, wherein the frame structure (Figs. 1/4C, 104, conductive pillars; the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) comprises a thermal expansion coefficient (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) higher than a thermal expansion coefficient (according to TopLine QFN CTE of silicon die chip, Si, 2.6x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the IC die (Fig. 1, 140, first die; mechanical chiplet, 120, e.g. silicon, [0016]) and lower than a thermal expansion coefficient (according to TopLine QFN CTE of molding compound, 30x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the molding compound layer (Figs. 4F/5, 150, [0031]).
Regarding Claim 6, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, wherein the frame structure comprises (Figs. 1/4C, 104, conductive pillars; the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) a thermal expansion coefficient of about 5 ppm/C to about 10 ppm/C (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026; 1ppm = 1x10-6; CuW and CuMo alloys have CTE about 6.5-8.5 and 7.0-9.0 respectively according to https://www.electronics-cooling.com/2007/02/thermal-conductivity-of-common-alloys-in-electronics-packaging/; accessed on 03/30/2026).
Regarding Claim 7, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, wherein the frame structure (Figs. 1/4C, 104, conductive pillars) comprises a metal frame structure (the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]).
Regarding Claim 8, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, wherein the frame structure (Figs. 1/4C, 104, conductive pillars) comprises copper, aluminum, nickel, or invar (the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]).
Regarding Claim 9, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, wherein a top surface (annotated Figure 1) of the frame structure (Figs. 1/4C, 104, conductive pillars) is substantially coplanar (annotated Figure 1) with a top surface (annotated Figure 1) of the molding compound layer (Figs. 1/4F, 150, [0031]).
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Regarding Claim 10, ZHONG teaches the structure (Fig. 1, 300, PoP structure) of claim 1, further comprising an adhesive layer (Figs. 4A-4F, 148) disposed between (annotated Figure 1) the frame structure (Figs. 1/4C, 104, conductive pillars) and the second bonding structure (annotated Figure 1).
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Regarding Claim 11, ZHONG teaches a structure (Fig. 1, 300, PoP structure), comprising:
first (Fig. 1, 140) and second IC dies (Fig. 1, 110);
first (annotated Figure 1) and second bonding structures (annotated Figure 1) disposed on the first (Fig. 1, 140) and second IC dies (Fig. 1, 110), respectively;
a third bonding structure bonded (annotated Figure 1) to the first (annotated Figure 1) and second bonding structures (annotated Figure 1) and disposed on a substrate (Fig. 4F, 102);
a molding compound layer (Figs. 1/4F, 150) surrounding each of the first (Fig. 1, 140) and second IC dies (Fig. 1, 110); and
a frame structure (Figs. 1/4C, 104, conductive pillars) surrounding each of the first (Fig. 1, 140) and second IC dies (Fig. 1, 140) and disposed in the molding compound layer (Figs. 1/4F, 150).
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Regarding Claim 12, ZHONG teaches the IC die package (Fig. 1, 300, PoP structure) of claim 11, wherein the frame structure (Figs. 1/4C, 104, conductive pillars; the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) comprises a thermal expansion coefficient (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) higher than thermal expansion coefficients (according to TopLine QFN CTE of silicon die chip, Si, 2.6x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the first and second IC dies (Fig. 1, 140/110, first die/second die; mechanical chiplet, 120, e.g. silicon, [0016]) and lower than a thermal expansion coefficient (according to TopLine QFN CTE of molding compound, 30x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the molding compound layer (Figs. 1/4F, 150, [0031]).
Regarding Claim 13, ZHONG teaches the IC die package (Fig. 1, 300, PoP structure) of claim 11, wherein the frame structure (Figs. 1/4C, 104, conductive pillars) comprises a metal frame structure (the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]).
Regarding Claim 14, ZHONG teaches the IC die package (Fig. 1, 300, PoP structure) of claim 11, wherein the frame structure (Figs. 1/4C, 104, conductive pillars) surrounds each of the first and second bonding structures (annotated Figure 1).
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Regarding Claim 15, ZHONG teaches the IC die package (Fig. 1, 300, PoP structure) of claim 11, wherein the frame structure (Figs. 1/4C, 104, conductive pillars) is attached to a top surface of the third bonding structure (annotated Figure 1).
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Regarding Claim 16, ZHONG teaches the IC die package (Fig. 1, 300, PoP structure) of claim 11, wherein the frame structure comprises (Figs. 1/4C, 104, conductive pillars; the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) a thermal expansion coefficient of about 5 ppm/C to about 10 ppm/C (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026; 1ppm = 1x10-6; CuW and CuMo alloys have CTE about 6.5-8.5 and 7.0-9.0 respectively according to https://www.electronics-cooling.com/2007/02/thermal-conductivity-of-common-alloys-in-electronics-packaging/; accessed on 03/30/2026).
Regarding Claim 17, ZHONG teaches a method (Figs. 1/4A-4F, 300, PoP structure), comprising:
forming a first bonding structure (annotated Figure 4B) on an integrated circuit (IC) die (Figs. 1/4B, 140, first die);
forming a second bonding structure (annotated Figure 4B) on an interposer die (Figs. 1/4B, 130, local interposer);
performing a bonding process between the first (annotated Figure 4B) and second bonding structures (annotated Figure 4B);
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attaching a frame structure (Figs. 1/4B-4F, 185/104, conductive pillars) on a top surface of the second bonding structure (annotated Figure 4B); and
performing a molding process (Figs. 1/4B-4F, 180/150) to form a molding compound layer (Figs. 1/4B-4F, 185/150) surrounding the IC die (Figs. 4B-4F/5, 140, first die) and the frame structure (Figs. 1/4B-4F, 185/104, conductive pillars).
Regarding Claim 18, ZHONG teaches the method (Figs. 1/4A-4F, 300, PoP structure) of claim 17, wherein attaching the frame structure (Figs. 1/4C, 104, conductive pillars) comprises attaching the frame structure (Figs. 1/4C, 104, conductive pillars) to the top surface with an epoxy layer or a die attach film (Figs. 4A-4F, 148/128/118).
Regarding Claim 19, ZHONG teaches the method (Figs. 1/4A-4F, 300, PoP structure) of claim 17, wherein attaching the frame structure (Figs. 1/4C, 104/185, conductive pillars) comprises placing a metal frame structure (the plurality of conductive pillars, 104/185 may be plated [0027]; plating by e.g. copper, [0032]) on the top surface of the second bonding structure (annotated Figure 4B).
Regarding Claim 20, ZHONG teaches the method (Figs. 1/4A-4F, 300, PoP structure) of claim 17, wherein performing the bonding process comprises performing a hybrid bonding process ([0026], [0028]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160163622 A1 – Figure 39
STATEMENT OF RELEVANCE – Schematic diagram of a packaging before-etching flip chip 3D system-in package metal circuit board structure.
US 20220052023 A1 – Figures 2A-2D
STATEMENT OF RELEVANCE – A portion of an example process flow for constructing chip for hybrid bonded interconnect bridging .
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812