DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1, 11, and 17 filed on 9/9/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 2-10, 12-16, and 18-20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 5-6, filed 06/12/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 102, or alternatively under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of YEH, and FENG.
Regarding Independent Claim(s) 1. Applicant traverses the rejection of previous office action that fails to disclose or suggest the amended features to claim 1, now recites, “a structure comprising: a frame structure disposed on the second bonding structure, wherein the frame structure forms an enclosure around the IC die in a plan view of the structure.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior art of YEH teaches in Figure 2, a schematic plan view, wherein the ring structure disposed on the package substrate, wherein the ring structure forms an enclosure around the semiconductor devices of a semiconductor die package.
Regarding Claims 2-16: The independent Claim(s) 11, and dependent claims 2-10, and 12-16 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Regarding Independent Claim(s) 17. Applicant traverses the rejection of previous office action that fails to disclose or suggest the amended features to claim 17, now recites, “a method, comprising: performing a bonding process between the third bonding structure…to bond a top surface…of the first and second bonding structures. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior art of FENG teaches in Figure 4E, a method comprising: performing a bonding process between the third bonding structure and the first and second bonding structures to bond a top surface of the third bonding structure to top surfaces of the first and second bonding structures.
Regarding Claims 18-20: The dependent claims 18-20 follow similar arguments as Claim 17, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chonghua Zhong et al, (hereinafter ZHONG), US 20200273843 A1, in view of Shu-Shen Yeh et al (hereinafter YEH), US 20230290702 A1.
Regarding Claim 1, ZHONG teaches a structure (Fig. 1, 300, PoP structure), comprising:
an integrated circuit (IC) die (Fig. 1, 140, first die)
an interposer die (Fig. 1, 130, vertical interposer) electrically connected (Fig. 4E, 171, routing to electrically connect the vertical interposer, 130 and first die, 140, [0033]) to the IC die (Fig. 1, 140, first die);
a first bonding structure (annotated Figure 1) disposed on the IC die (Fig. 1, 140, first die);
a second bonding structure (annotated Figure 1) bonded to the first bonding structure (annotated Figure 1);
a molding compound layer (Figs. 1/4F, 150) disposed on the second bonding structure (annotated Figure 1); and
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Though ZHONG teaches a frame structure disposed on the second bonding structure; and surrounding the IC die, ZHONG does not explicitly disclose a structure, comprising: a frame structure disposed on the second bonding structure, wherein the frame structure forms an enclosure around the IC die in a plan view of the structure.
YEH teaches a structure (Figs. 1A-1F, semiconductor die package, [0022]), comprising: a frame structure (Figs. 1F-2/2, 130, ring structure) disposed on the second bonding structure (Figs. 1F-2/2, 120, package substrate), wherein the frame structure (Figs. 1F-2/2, 130, ring structure) forms an enclosure around the IC die (Figs. 1F-2/2, 110/112, semiconductor devices) in a plan view of the structure (Fig. 2, the ring structure, 130 surrounds the semiconductor devices, 110, and 112, [0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHONG to incorporate the teachings of YEH, such that a structure, comprising: a frame structure disposed on the second bonding structure, wherein the frame structure forms an enclosure around the IC die in a plan view of the structure, so that the ring structure surrounding the IC die reduces stresses or warpage and enhance the robustness of the semiconductor package (YEH, [0049-0050]).
Regarding Claim 2, ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars) surrounds the first bonding structure (annotated Figure 1).
Regarding Claim 3, ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars, [0031]) is disposed in the molding compound layer (Figs. 1/4F, 150, [0031]).
Regarding Claim 4, ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars) comprises (the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) a thermal expansion coefficient lower (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) than a thermal expansion coefficient (according to TopLine QFN CTE of molding compound, 30x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the molding compound layer (Figs. 1/4F, 150, [0031]).
Regarding Claim 5, ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars; the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) comprises a thermal expansion coefficient (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) higher than a thermal expansion coefficient (according to TopLine QFN CTE of silicon die chip, Si, 2.6x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the IC die (Fig. 1, 140, first die; mechanical chiplet, 120, e.g. silicon, [0016]) and lower than a thermal expansion coefficient (according to TopLine QFN CTE of molding compound, 30x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the molding compound layer (Figs. 4F/5, 150, [0031]).
Regarding Claim 6, ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), wherein the frame structure comprises (Figs. 1/4C, 104, conductive pillars; the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) a thermal expansion coefficient of about 5 ppm/C to about 10 ppm/C (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026; 1ppm = 1x10-6; CuW and CuMo alloys have CTE about 6.5-8.5 and 7.0-9.0 respectively according to https://www.electronics-cooling.com/2007/02/thermal-conductivity-of-common-alloys-in-electronics-packaging/; accessed on 03/30/2026).
Regarding Claim 7, ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars) comprises a metal frame structure (the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]).
Regarding Claim 8 ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars) comprises copper, aluminum, nickel, or invar (the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]).
Regarding Claim 9, ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), wherein a top surface (annotated Figure 1) of the frame structure (Figs. 1/4C, 104, conductive pillars) is substantially coplanar (annotated Figure 1) with a top surface (annotated Figure 1) of the molding compound layer (Figs. 1/4F, 150, [0031]).
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Regarding Claim 10 ZHONG as modified by YEH teaches the structure of claim 1.
ZHONG further teaches the structure (Fig. 1, 300, PoP structure), further comprising an adhesive layer (Figs. 4A-4F, 148) disposed between (annotated Figure 1) the frame structure (Figs. 1/4C, 104, conductive pillars) and the second bonding structure (annotated Figure 1).
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Claim(s) 11-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHONG, in view of YEH as applied to Claim(s) 1-10, and further in view of Hongxia Feng et al, (hereinafter FENG), US 20230317653 A1.
Regarding Claim 11, ZHONG teaches a structure (Fig. 1, 300, PoP structure), comprising:
first (Fig. 1, 140) and second IC dies (Fig. 1, 110);
first (annotated Figure 1) and second bonding structures (annotated Figure 1) disposed on the first (Fig. 1, 140) and second IC dies (Fig. 1, 110), respectively;
a third bonding structure bonded (annotated Figure 1) to the first (annotated Figure 1) and second bonding structures (annotated Figure 1) and disposed on a substrate (Fig. 4F, 102);
a molding compound layer (Figs. 1/4F, 150) surrounding each of the first (Fig. 1, 140) and second IC dies (Fig. 1, 110); and
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Though ZHONG teaches a frame structure surrounding each of the first and second IC dies disposed in the molding compound layer, ZHONG does not explicitly disclose a structure, comprising: a frame structure disposed on in the molding compound layer, wherein the frame structure forms an enclosure around each of the first and second IC dies in a plan view of the IC die package.
YEH teaches a structure (Figs. 1A-1F, semiconductor die package, [0022]), comprising: a frame structure (Figs. 1F-2/2, 130, ring structure), wherein the frame structure (Figs. 1F-2/2, 130, ring structure) forms an enclosure around each of the first and second IC dies (Figs. 1F-2/2, 110/112, semiconductor devices) in a plan view of the IC die package (Fig. 2, the ring structure, 130 surrounds the semiconductor devices, 110, and 112, [0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHONG to incorporate the teachings of YEH, such that a structure, comprising: a frame structure disposed on in the molding compound layer, wherein the frame structure forms an enclosure around each of the first and second IC dies in a plan view of the IC die package, so that the ring structure surrounding the IC die reduces stresses or warpage and enhance the robustness of the semiconductor package (YEH, [0049-0050]).
ZHONG as modified by YEH does not explicitly disclose a structure, comprising: a frame structure disposed on in the molding compound layer.
FENG teaches a structure (Fig. 1A, 100a1/100a2, package, [0023]), comprising: a frame structure (Figs. 4C/4E, 444, copper pillars) disposed on in the molding compound layer (Figs. 4C/4E, 460, mold).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHONG as modified by YEH to incorporate the teachings of FENG, such that a structure, comprising: a frame structure disposed on in the molding compound layer, so that the mold may include any molding compound that may provide good encapsulation performance and good mechanical reliability (FENG, [0039]).
Regarding Claim 12, ZHONG as modified by YEH and FENG teaches the IC die package of claim 11.
ZHONG further teaches the IC die package (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars; the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) comprises a thermal expansion coefficient (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) higher than thermal expansion coefficients (according to TopLine QFN CTE of silicon die chip, Si, 2.6x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the first and second IC dies (Fig. 1, 140/110, first die/second die; mechanical chiplet, 120, e.g. silicon, [0016]) and lower than a thermal expansion coefficient (according to TopLine QFN CTE of molding compound, 30x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026) of the molding compound layer (Figs. 1/4F, 150, [0031]).
Regarding Claim 13, ZHONG as modified by YEH and FENG teaches the IC die package of claim 11.
ZHONG further teaches the IC die package (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars) comprises a metal frame structure (the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]).
Regarding Claim 14, ZHONG as modified by YEH and FENG teaches the IC die package of claim 11.
ZHONG further teaches the IC die package (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars) surrounds each of the first and second bonding structures (annotated Figure 1).
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Regarding Claim 15, ZHONG as modified by YEH and FENG teaches the IC die package of claim 11.
ZHONG further teaches the IC die package (Fig. 1, 300, PoP structure), wherein the frame structure (Figs. 1/4C, 104, conductive pillars) is attached to a top surface of the third bonding structure (annotated Figure 1).
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Regarding Claim 16, ZHONG as modified by YEH and FENG teaches the IC die package of claim 11.
ZHONG further teaches the IC die package (Fig. 1, 300, PoP structure), wherein the frame structure comprises (Figs. 1/4C, 104, conductive pillars; the plurality of conductive pillars, 104 may be plated [0027]; plating by e.g. copper, [0032]) a thermal expansion coefficient of about 5 ppm/C to about 10 ppm/C (according to TopLine QFN CTE of Lead Frame Base Alloy involving Cu, 16.7x10-6 /oC; https://www.topline.tv/CTE_QFN.html; accessed on 03/30/2026; 1ppm = 1x10-6; CuW and CuMo alloys have CTE about 6.5-8.5 and 7.0-9.0 respectively according to https://www.electronics-cooling.com/2007/02/thermal-conductivity-of-common-alloys-in-electronics-packaging/; accessed on 03/30/2026).
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over FENG as applied to Claim(s) 11-16, and in view of ZHONG, as applied to Claim(s) 1-10.
Regarding Claim 17, FENG teaches a method (Fig. 6, 600, process), comprising:
forming first and second bonding structures structure (annotated Figure 4D) on an integrated circuit (IC) die (Figs. 4A/4D, 420);
forming a third bonding structure (annotated Figure 4D) on an interposer die (Fig. 4D, 442, substrate layer);
performing a bonding process between the third bonding structure (annotated Figure 4D) and the first and second bonding structures (annotated Figure 4D) to bond a top surface of the third bonding structure (annotated Figure 4D) to top surfaces of the first and second bonding structures (annotated Figure 4D);
attaching a frame structure (Fig. 4D, 444, copper pillars) on the top surface of the third bonding structure (annotated Figure 4D); and
performing a molding process to form a molding compound layer (Figs. 4C/4D, 460, mold) surrounding the IC die (Figs. 4A/4D, 420) and the frame structure (Fig. 4D, 444, copper pillars).
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Though FENG teaches a method, comprising: attaching a frame structure on the top of the substrate layer, FENG does not explicitly disclose a method, comprising: attaching a frame structure on the top surface of the third bonding structure.
ZHONG teaches a method (Fig. 3, flow chart illustrating a sequence of forming a package structure, [0025]), comprising:
attaching a frame structure (Figs. 1, 185, conductive pillars) on a top surface of the third bonding structure (Fig. 1, 160, wiring layers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified FENG to incorporate the teachings of ZHONG, such that a method, comprising: attaching a frame structure on the top surface of the third bonding structure, so that the vertical interposers are electrically connected with the stacked semiconductor dies (ZHONG, [0016]).
Regarding Claim 18, FENG as modified by ZHONG teaches the method of claim 17.
ZHONG further teaches the method (Fig. 3, flow chart illustrating a sequence of forming a package structure, [0025]), wherein attaching the frame structure (Figs. 1/4C, 104, conductive pillars) comprises attaching the frame structure (Figs. 1/4C, 104, conductive pillars) to the top surface with an epoxy layer or a die attach film (Figs. 4A-4F, 148/128/118).
Regarding Claim 19, FENG as modified by ZHONG teaches the method of claim 17.
ZHONG further teaches the method (Fig. 3, flow chart illustrating a sequence of forming a package structure, [0025]), wherein attaching the frame structure (Figs. 1/4C, 104/185, conductive pillars) comprises placing a metal frame structure (the plurality of conductive pillars, 104/185 may be plated [0027]; plating by e.g. copper, [0032]) on the top surface of the second bonding structure (annotated Figure 4B).
Regarding Claim 20, FENG as modified by ZHONG teaches the method of claim 17.
ZHONG further teaches the method (Fig. 3, flow chart illustrating a sequence of forming a package structure, [0025]), wherein performing the bonding process comprises performing a hybrid bonding process ([0026], [0028]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230378024 A1 – Figure 2A
STATEMENT OF RELEVANCE – The first ring structure, 214 and the second ring structure, 218 dimensioned to surround the semiconductor dies, 204a, and 204b and the molding, 208.
US 20230066752 A1 – Figure 1
STATEMENT OF RELEVANCE – the ring structure 30 can be placed (for example, using a pick-and-place tool, not shown) over the surface 10 A, and is arranged along the periphery of the package substrate 10 to surround the package component 20 (as well as the semiconductor dies 22 and 22 ′).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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