DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/06/2023, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim et al. (US 20230106015) herein referred to as Kim. (Figs. 1, 8A)
As to claim 1, Kim teaches a method comprising:
forming a first set of trenches (trench is filled by 110, Fig. 8A), in a semiconductor structure ([0019] semiconductor device 100, Fig 1) wherein forming
the first set of trenches (trench is filled by 110, Fig. 8A) further forms a first set of fin structures fins ([0022] Each of the active regions 105 may include active fins protruding upwardly);
depositing outer shallow trench isolation material ([0024] Annotated outer shallow trench isolation 192, Fig. 8A) in the first set of trenches;
depositing inner shallow trench isolation material ([0024] Annotated inner shallow trench isolation 110, Fig. 8A) over the outer shallow trench isolation material in the first set of trenches;
forming a gate ([0019] gate structure 160, Fig. 8A) based on the first set of trenches and the first set of fin structures; and
forming power rail connections ([0038] interconnection line 180) in contact with the gate (gate 160 See Fig. 5A) and the outer shallow trench isolation material, wherein
a signal wire ([0041] lower contact plug (144) Fig 8A) connection of the power rail connections is in contact with a gate extension region (Annotated gate extension, Fig 8A) of the gate.
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Allowable Subject Matter
Claims 2-10 and 11 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art, Kim, taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art Kim (Figs. 1, 5A and 8A) fails to teach a combination of all of the features in the claims.
As to claim 2, Kim teaches the method of claim 1, wherein
the semiconductor structure ([0019] semiconductor device 100, Fig 1) includes: a silicon substrate ([0020] The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like).;
a first sacrificial layer ([0110]”The sacrificial dielectric layer 220 may be selectively removed with respect to the first interlayer insulating layer 192.) disposed on the silicon substrate (101),
However, Kim fails to teach the following relationships: wherein
a silicon etch stop disposed on the silicon layer, wherein
the silicon etch stop includes SiGe55%;
the first sacrificial layer includes SiGe25%;
a silicon layer disposed on the first sacrificial layer
a plurality of sacrificial layers disposed through the device etch stop layer, a second sacrificial layer, a first nanosheet, a third sacrificial layers, a second nanosheet and a fourth sacrificial layer.
As to claim 11, Kim teaches a semiconductor structure, comprising:
a set of backside source/drain contacts ([0041] contact plug 142), wherein the set of backside source/drain contacts include a first backside source/drain contact ([0043]The line region 142L may be disposed to extend in a predetermined length in one direction, for example, in a Y direction, to connect the adjacent source/drain regions 130, Annotated 1st source drain contact 142L) , a second backside source/drain contact (Annotated 2nd source drain contact 142L), and a third backside source/drain contact (Annotated 3rd source drain contact 142L);
a gate ([0019] gate structure 160, Fig. 8A) that includes a gate extension region (Annotated gate extension, Fig 8A);
power rail connections ([0038] interconnection line 180) that include a signal wire connection ([0041] lower contact plug (144) Fig 8A) in contact with the gate extension region (Annotated gate extension, Fig 8A) and a first interlayer dielectric ([0055] substrate insulating layer 107), wherein
the gate extension region (Annotated gate extension, Fig 8A) extends from the gate (gate 160 See Fig. 8A) to the signal wire connection ([0041] lower contact plug (144) Fig 8A), and wherein
However, Kim fails to teach the following relationships:
the signal wire connection is electrically isolated from the second backside source/drain contact and the third backside source/drain contact; and
signal wire spacers disposed on sides of the signal wire connection, wherein
the signal wire spacers are in contact with the first interlayer dielectric, an extended interlayer dielectric, the second backside source/drain contact, and the third backside source/drain contact.
The remaining claims 12-20 are allowable at least because they depend from allowable independent claim 11. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897