DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(1) as being clearly anticipated by Park; Heat Bit et al. (US 2018/0374779; hereinafter Park). Regarding claim 1, Park discloses a semiconductor die (22; Fig 2; ¶ [0029]) , comprising: a substrate (that through which a via 23 extends; Fig 2) , wherein the substrate comprises a top surface (upper surface, facing away from 21; Fig 2) and a bottom surface (lower surface, facing 21; Fig 2) arranged opposite to the top surface; and a plurality of pairs of signal via groups (G0; Figs 2,3; ¶ [0037-39[) which are independent of each other, wherein a plurality of signal via groups are arranged in the substrate and spaced apart from each other (as shown in Figs 2,4A) , two signal via groups in each pair of the plurality of pairs of signal via groups are distributed symmetrically with respect to an axis located on the top surface of the substrate (with respect an axis mid-way between any two G0 denoted by dotted lines in Fig 4A, the axis extending in either the x- or y- direction) , one of the two signal via groups is distributed in a first region arranged on one side of the axis, and another one of the two signal via groups is distributed in a second region arranged on another side of the axis, the axis being parallel to a first direction or a second direction, each of the plurality of signal via groups comprises a plurality of signal vias (310,312,314,316; Fig 4A; ¶ [0039]) arranged in a polygonal shape (as shown in Fig 4A; ¶ [0038]) , any two of the plurality of signal vias in each of the plurality of signal via groups are electrically isolated from each other (in order for the device to function as intended) , each of the plurality of signal vias penetrates through the substrate along a third direction (z- direction; vertically, as shown in Fig 2; ¶ [0035]) , wherein the first direction and the second direction are perpendicular to each other and are parallel to the top surface of the substrate, and the third direction is a direction perpendicular to the top surface of the substrate. Regarding claim 6 , Park discloses the semiconductor die according to claim 1, wherein each of the plurality of signal via groups (G0; Fig 4A) comprises four signal vias (310,312,314,316; Fig 4A; ¶ [0039]) , and the four signal vias are arranged in a square shape or a diamond shape (as shown in Fig 4A; ¶ [0038]) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 - 5 are rejected under 35 U.S.C. 103 as being unpatentable over Park; Heat Bit et al. (US 2018/0374779; hereinafter Park) in view of Nin; Shu-Liang (US 2012/0267776; hereinafter Nin). Regarding claim 2, Park discloses the semiconductor die according to claim 1, but does not disclose the further limitation of claim 2. In the same field of endeavor, Nin discloses a similar semiconductor die (400 {400a }; Figs 2-5; ¶ [0020- 33 ]) comprising: a plurality of top metal interconnection structures (404 {404I}; Figs 3-5; ¶ [0021-24]) , wherein the plurality of top metal interconnection structures are located on the top surface of the substrate (RDL; ¶ [0021]) , each of the plurality of top metal interconnection structures comprises a plurality of conductive paths ( Nin; 500; Fig 2; ¶ [0020]); and comprising 406,408,410; Figs 3,4{unlabeled},5; ¶ [0021-22]). That is, Park and Nin disclose similar die, wherein Park does not disclose the plurality of top metal interconnection structures and Nin does not disclose the vias comprise signal via groups. Accordingly, it would have been obvious for a person having ordinary skill in the art to have combined the plurality of top metal interconnection structures of Nin with the disclosure of Park as applied to claim 1 such that each of the plurality of top metal interconnection structures (Nin) corresponds to and is electrically connected to a respective one of the plurality of signal via groups (Park) , and each of the plurality of conductive paths (Nin) corresponds to and is electrically connected to a respective one of the plurality of signal vias (Nin, Park) in the respective one of the plurality of signal via groups (Park) . One would have been motivated to do this as a means of connection (at least as an alternate means) from one die to another in a stacked configuration as disclosed by both Park (Fig s 2, 5; ¶ [0048-50]) and Nin (Figs 2,4; ¶ [0020-21]) ; details of the connection means to implement a spiral shaped connection as disclosed by Park (Fig 5; ¶ [0049]) are unclear to the Examiner , and Nin provides a means (Nin; Fig s 2,4; ¶ [0028]) . One would have had a reasonable expectation of success because of the similar structures of both Park and Nin. Regarding claim 3 , Park in view of Nin discloses the semiconductor die according to claim 2 , wherein each of the plurality of top metal interconnection structures (Nin; (404 {404I}; Figs 3-5) comprises: a first conductive layer (Nin; 406; Fig 3; ¶ [0021]), wherein the first conductive layer is located on the top surface of the substrate and comprises a plurality of first conductive elements (Nin; 406a I, 406a II, 406a III, 406a IV; Fig 4 {only 404a I, 404b II, 404c III, and 404d IV are labeled}]; ¶ [0024-25]) spaced apart from each other, the plurality of first conductive elements are arranged in the polygonal shape (Nin; as shown in Fig 4, and corresponding the square shape of the TSV’s 402; ¶ [0025]) , and each of the plurality of first conductive elements corresponds to and is electrically connected to a respective one of the plurality of signal vias in the respective one of the plurality of signal via groups (Nin; ¶ [0025]) ; a second conductive layer (Nin; 4 10 ; Fig 3; ¶ [0021]) , wherein the second conductive layer is located on the first conductive layer and comprises a plurality of second conductive elements (unlabeled, analogous to 406a I, 406a II, 406a III, 406a IV for the layer 408; Figs 3,4) spaced apart from each other, each of the plurality of second conductive elements corresponds to a respective one of the plurality of first conductive elements, the plurality of second conductive elements are arranged in the polygonal shape, and a portion of each of the plurality of second conductive elements is overlapped with a portion of the respective one of the plurality of first conductive elements (Nin; Figs 3,4; ¶ [0021-25]) ; and a plurality of connection elements (Nin; 408; Fig 3; ¶ [0021]) , wherein each of the plurality of connection elements corresponds to a respective one of the plurality of first conductive elements and a respective one of the plurality of second conductive elements, and each of the plurality of connection elements is configured to electrically connect the respective one of the plurality of first conductive elements with the respective one of the plurality of second conductive elements, to form a respective one of the plurality of conductive paths (Nin; Figs 3,4,5; ¶ [0021-25]) . Regarding claim 4 , Park in view of Nin discloses the semiconductor die according to claim 3 , wherein each of the plurality of first conductive elements (Nin; 406, including 406a I, 406a II, 406a III, 406a IV; Figs 3,4) comprises a first end and a second end (a left end of 406 , over a respective 402 {402 I} , and a right end of 406 , under a respective 408, respectively, as shown in Fig 3) , the first end being arranged opposite to the second end along an extension direction of said each of the plurality of first conductive elements, and each of the plurality of second conductive elements (Nin; 410; Figs 3,4), comprises a third end and a fourth end (a left end of 410, over a respective 408, and a right end, over an adjacent 402 {402 II}, respectively, as shown in Fig 3) , the third end being arranged opposite to the fourth end along an extension direction of said each of the plurality of second conductive elements; wherein the first end of each of the plurality of first conductive elements corresponds to and is electrically connected to the respective one of the plurality of signal vias (as shown in Nin Fig 3, and as applied to claim 3) ; and wherein for each of the plurality of second conductive elements and the respective one of the plurality of first conductive elements, an end of a respective one of the plurality of connection elements (Nin; 408; Fig 3) is electrically connected to the third end of said each of the plurality of second conductive elements, and another end of the respective one of the plurality of connection elements is electrically connected to the second end of the respective one of the plurality of first conductive elements (Nin; as shown in Fig 3; ¶ [0021]) . Regarding claim 5 , Park in view of Nin discloses the semiconductor die according to claim 3 , further comprising: a plurality of internal circuits (Park; data transmission circuit 421 , comprising 421_0 to 421_32 ; Fig s 3 ,6A ; ¶ [0054- 58,0067-70]) , wherein each of the plurality of internal circuits corresponds to a respective one of the plurality of top metal interconnection structures (Nin; (404 {404I}; Figs 3-5) , and each of the plurality of internal circuits is electrically connected to a respective one of the plurality of conductive paths in the respective one of the plurality of top metal interconnection structures (Park; for example 421_0 corresponds to one via/path; ¶ [0069]) ; and a plurality of lead-out wires, wherein each of the plurality of lead-out wires corresponds to a respective one of the plurality of internal circuits, an end of each of the plurality of lead-out wires is electrically connected to the respective one of the plurality of internal circuits, and another end of each of the plurality of lead-out wires is only electrically connected to a respective one of the plurality of first conductive elements in the respective one of the plurality of top metal interconnection structures (as indicated in Fig 6A of Park, and being obvious to a person having ordinary skill in the art that a wire must connect in this fashion in order for the circuit and device to function; the combination of elements between Park and Nin being further obvious as applied to claims 2 and 3 due to the similarity in the disclosures of Park and Nin as noted under claim 2) . Claims 7- 8 , 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park; Heat Bit et al. (US 2018/0374779; hereinafter Park) in view of Oh; Tae-young et al. ( US 2011 / 0309468 ; hereinafter Oh ). Regarding claim 7 , Park discloses a semiconductor device (2; Fig 2; ¶ [0029-32]) , comprising: a base plate (21; Fig 2; ¶ [0030]) ; and a stack structure (Fig 2; ¶ [0029]) , wherein the stack structure is located on the base plate and comprises N cell structures (22; Fig 2; ¶ [0029-32]) , the N cell structures are sequentially stacked on one another in a third direction (z- direction; vertically, as shown in Fig 2; ¶ [0035]) and are electrically connected to each other (¶ [0029]), each of the N cell structures comprises four semiconductor dies (Figs 2,3; ¶ [0034]), wherein N is a positive integer, wherein each of the four semiconductor dies comprises: a substrate (that through which a via 23 extends; Fig 2), wherein the substrate comprises a top surface (upper surface, facing away from 21; Fig 2) and a bottom surface (lower surface, facing 21; Fig 2) arranged opposite to the top surface; and a plurality of pairs of signal via groups (G0; Figs 2,3; ¶ [0037-39[) which are independent of each other, wherein a plurality of signal via groups are arranged in the substrate and spaced apart from each other (as shown in Figs 2,4A), two signal via groups in each pair of the plurality of pairs of signal via groups are distributed symmetrically with respect to an axis located on the top surface of the substrate (with respect an axis mid-way between any two G0 denoted by dotted lines in Fig 4A, the axis extending in either the x- or y- direction), one of the two signal via groups is distributed in a first region arranged on one side of the axis, and another one of the two signal via groups is distributed in a second region arranged on another side of the axis, the axis being parallel to a first direction or a second direction, each of the plurality of signal via groups comprises a plurality of signal vias (310,312,314,316; Fig 4A; ¶ [0039]) arranged in a polygonal shape (as shown in Fig 4A; ¶ [0038]), any two of the plurality of signal vias in each of the plurality of signal via groups are electrically isolated from each other (in order for the device to function as intended), each of the plurality of signal vias penetrates through the substrate along the third direction , wherein the first direction and the second direction are perpendicular to each other and are parallel to the top surface of the substrate, and the third direction is a direction perpendicular to the top surface of the substrate ; wherein the four semiconductor dies in each of the N cell structures are sequentially stacked on one another along the third direction (¶ [0036]). Park does not disclose: a first semiconductor die at a bottommost layer of the four semiconductor dies is stacked face-to-face with a second semiconductor die arranged above the first semiconductor die, the second semiconductor die is stacked back-to-back with a third semiconductor die arranged above the second semiconductor die, and the third semiconductor die is stacked face-to-face with a fourth semiconductor die arranged above the third semiconductor die; wherein axes of any two adjacent semiconductor dies of a plurality of semiconductor dies in the stack structure are aligned with each other, and the first region of one of the any two adjacent semiconductor dies is aligned with the second region of another one of the any two adjacent semiconductor dies , and wherein face-to-face means that top surfaces of two adjacent semiconductor dies face towards each other, and back-to-back means that bottom surfaces of two adjacent semiconductor dies face towards each other. In the same field of endeavor, Oh discloses a similar semiconductor device ( 5 00 {stacked like 200} ; Fig 3 {2} ; ¶ [00 77 - 94 { 00 8 1} ], entire document), wherein a first semiconductor die (220; Fig 2) at a bottommost layer of the four semiconductor dies is stacked face-to-face with a second semiconductor die (230; Fig 2) arranged above the first semiconductor die (Fig 2; ¶ [0041]), wherein axes of any two adjacent semiconductor dies (220,230; Fig 2) of a plurality of semiconductor dies in the stack structure are aligned with each other, and the first region of one of the any two adjacent semiconductor dies is aligned with the second region of another one of the any two adjacent semiconductor dies (rotated 180 degrees and having aligned vias; ¶ [0041]) . It would have been obvious to a person having ordinary skill in the art to arrange the bottommost pair of die of Park in the face-to-face manner disclosed by Oh, and to stack the second pair of die comprising the four-die cell structure in the same face-to-face fashion with one another, requiring a back-to-back arrangement of one die from each pair with one another to complete the four die stack, while maintaining the channel/via alignment disclosed by Park in Figs 4A-4D and 5, and associated description, and thereby satisfy the further limitations of claim 7. One would have been motivated to do this in consideration of various design , performance , and manufacturing requirements for a particular application. One would have had a reasonable expectation of success because of the similar structures of Park and Oh , and because the various and finite die stacking orientations are known in the art . Regarding claim 8 , Park in view of Oh discloses a semiconductor device according to claim 7, further comprising: a plurality of pairs of signal transmission link groups, wherein each pair of the plurality of pairs of signal transmission link groups corresponds to a respective one of the plurality of pairs of signal via groups in each of the plurality of semiconductor dies, each of a plurality of signal transmission link groups comprises a plurality of signal transmission links ( Park; the spiral transmission paths shown by CH0,CH1,CH2,CH3; Fig 5; ¶ [0048-49]) , the plurality of signal transmission links in each of the plurality of signal transmission link groups are independent of each other and each spirally extend along the third direction, each of the plurality of signal transmission links in each of the plurality of signal transmission link groups corresponds to a respective one of the plurality of signal vias in a respective one of the plurality of signal via groups in each of the plurality of semiconductor dies, and each of the plurality of signal transmission links comprises the respective one of the plurality of signal vias in each of the plurality of semiconductor dies. (Park; the limitations of claim 8 are disclosed by Fig 5; ¶ [0048-49] and the additional description and drawings as applied to claim 7, wherein Park’s spiral transmission paths {Fig. 5} corresponding to signal vias (310,312,314,316; Fig s 4A -4D) in each of the stacked die may be grouped to correspond to the lim it ations ) . Regarding claim 15 , Park discloses a method for forming semiconductor device (2; Fig 2; ¶ [0029-32]) , comprising: providing a base plate (21; Fig 2; ¶ [0030]) ; and forming a plurality of semiconductor dies (22; Figs 2,3; ¶ [0029-34]), wherein each of the plurality of semiconductor dies comprises a substrate (that through which a via 23 extends; Fig 2) , and a plurality of pairs of signal via groups (G0; Figs 2,3; ¶ [0037-39 ] ) which are independent of each other , wherein the substrate comprises a top surface (upper surface, facing away from 21; Fig 2) and a bottom surface (lower surface, facing 21; Fig 2) arranged opposite to the top surface; and a plurality of signal via groups are arranged in the substrate and spaced apart from each other (as shown in Figs 2,4A), two signal via groups in each pair of the plurality of pairs of signal via groups are distributed symmetrically with respect to an axis located on the top surface of the substrate (with respect an axis mid-way between any two G0 denoted by dotted lines in Fig 4A, the axis extending in either the x- or y- direction), one of the two signal via groups is distributed in a first region arranged on one side of the axis, and another one of the two signal via groups is distributed in a second region arranged on another side of the axis, the axis being parallel to a first direction or a second direction, each of the plurality of signal via groups comprises a plurality of signal vias (310,312,314,316; Fig 4A; ¶ [0039]) arranged in a polygonal shape (as shown in Fig 4A; ¶ [0038]), any two of the plurality of signal vias in each of the plurality of signal via groups are electrically isolated from each other (in order for the device to function as intended), each of the plurality of signal vias penetrates through the substrate along a third direction (z- direction; vertically, as shown in Fig 2; ¶ [0035]) , wherein the first direction and the second direction are perpendicular to each other and are parallel to the top surface of the substrate, and the third direction is a direction perpendicular to the top surface of the substrate ; and forming a stack structure (Fig 2; ¶ [0029]) , wherein the stack structure on the base plate based on the plurality of semiconductor dies, wherein the stack structure comprises N cell structures (22; Fig 2; ¶ [0029-32]) , the N cell structures are sequentially stacked on one another in the third direction and are electrically connected to each other (¶ [0029]), each of the N cell structures comprises four semiconductor dies (Figs 2,3; ¶ [0034]), the four semiconductor dies in each of the N cell structures are sequentially stacked on one another along the third direction (¶ [0036]). Park does not disclose: a first semiconductor die at a bottommost layer of the four semiconductor dies is stacked face-to-face with a second semiconductor die arranged above the first semiconductor die, the second semiconductor die is stacked back-to-back with a third semiconductor die arranged above the second semiconductor die, and the third semiconductor die is stacked face-to-face with a fourth semiconductor die arranged above the third semiconductor die , wherein N is a positive integer, wherein axes of any two adjacent semiconductor dies of the plurality of semiconductor dies in the stack structure are aligned with each other, and the first region of one of the any two adjacent semiconductor dies is aligned with the second region of another one of the any two adjacent semiconductor dies, and wherein face-to-face means that top surfaces of two adjacent semiconductor dies face towards each other, and back-to-back means that bottom surfaces of two adjacent semiconductor dies face towards each other. In the same field of endeavor, Oh discloses a similar semiconductor device ( 5 00 {stacked like 200}; Fig 3 {2}; ¶ [00 77 - 94 {00 8 1}], entire document), wherein a first semiconductor die (220; Fig 2) at a bottommost layer of the four semiconductor dies is stacked face-to-face with a second semiconductor die (230; Fig 2) arranged above the first semiconductor die (Fig 2; ¶ [0041]), wherein axes of any two adjacent semiconductor dies (220,230; Fig 2) of a plurality of semiconductor dies in the stack structure are aligned with each other, and the first region of one of the any two adjacent semiconductor dies is aligned with the second region of another one of the any two adjacent semiconductor dies (rotated 180 degrees and having aligned vias; ¶ [0041]). It would have been obvious to a person having ordinary skill in the art to arrange the bottommost pair of die of Park in the face-to-face manner disclosed by Oh, and to stack the second pair of die comprising the four-die cell structure in the same face-to-face fashion with one another, requiring a back-to-back arrangement of one die from each pair with one another to complete the four die stack, while maintaining the channel/via alignment disclosed by Park in Figs 4A-4D and 5, and associated description, and thereby satisfy the further limitations of claim 7. One would have been motivated to do this in consideration of various design, performance, and manufacturing requirements for a particular application. One would have had a reasonable expectation of success because of the similar structures of Park and Oh , and because the various and finite die stacking orientations are known in the art . Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park; Heat Bit et al. (US 2018/0374779; hereinafter Park) in view of Oh; Tae-young et al. (US 2011/0309468; hereinafter Oh), and further in view of F ang ; Hsu-Nan ( US 2022 / 0199559 ; hereinafter Fang). Regarding claim 9, Park in view of Oh discloses a semiconductor device according to claim 8, but does not disclose further comprising: a plurality of pairs of bonding pillar groups, wherein the plurality of pairs of bonding pillar groups are located only between any two adjacent semiconductor dies stacked face-to-face with each other, each pair of the plurality of pairs of bonding pillar groups corresponds to a respective one of the plurality of pairs of signal via groups in each of the any two adjacent semiconductor dies stacked face-to-face with each other, to implement signal transmission between the any two adjacent semiconductor dies stacked face-to-face with each other, each of a plurality of bonding pillar groups comprises a plurality of bonding pillars, each of the plurality of bonding pillars corresponds to a respective one of the plurality of signal vias in each of the any two adjacent semiconductor dies stacked face-to-face with each other; and wherein each pair of the plurality of pairs of signal transmission link groups corresponds to a respective one of the plurality of pairs of bonding pillar groups located between the any two adjacent semiconductor dies stacked face-to-face with each other, each of the plurality of signal transmission links in each of the plurality of signal transmission link groups corresponds to a respective one of the plurality of bonding pillars in the respective one of the plurality of pairs of bonding pillar groups, and each of the plurality of signal transmission links comprises the respective one of the plurality of bonding pillars arranged between the any two adjacent semiconductor dies stacked face-to-face with each other. In the same field of endeavor Fang discloses a semiconductor device comprising stacked semiconductor die (110,210; Fig 8D; ¶ [ 0091, 0021]) connected by bonding pillars (120,220; Fig 8D; ¶ [0091]). Accordingly, it would have been obvious to a person having ordinary skill in the art to include similar bonding pillars between the stacked die of Park in view of Oh according to claim 8 , such that the semiconductor device further comprises: a plurality of pairs of bonding pillar groups, wherein the plurality of pairs of bonding pillar groups are located only between any two adjacent semiconductor dies stacked face-to-face with each other (as may be required according to design performance and/or manufacturing requirements that may be required for a particular application) , each pair of the plurality of pairs of bonding pillar groups corresponds to a respective one of the plurality of pairs of signal via groups in each of the any two adjacent semiconductor dies stacked face-to-face with each other (in order to facilitate connection s to maintain a plurality of spiral transmission path s disclosed by Park { CH0,CH1,CH2,CH3; Fig 5; ¶ [0048-49] ) , to implement signal transmission between the any two adjacent semiconductor dies stacked face-to-face with each other, each of a plurality of bonding pillar groups comprises a plurality of bonding pillars, each of the plurality of bonding pillars corresponds to a respective one of the plurality of signal vias in each of the any two adjacent semiconductor dies stacked face-to-face with each other (Park; ¶ [0048-49]) ; and wherein each pair of the plurality of pairs of signal transmission link groups corresponds to a respective one of the plurality of pairs of bonding pillar groups located between the any two adjacent semiconductor dies stacked face-to-face with each other, each of the plurality of signal transmission links in each of the plurality of signal transmission link groups corresponds to a respective one of the plurality of bonding pillars in the respective one of the plurality of pairs of bonding pillar groups, and each of the plurality of signal transmission links comprises the respective one of the plurality of bonding pillars arranged between the any two adjacent semiconductor dies stacked face-to-face with each other (in order to facilitate connections to maintain a plurality of spiral transmission paths disclosed by Park { CH0,CH1,CH2,CH3; Fig 5; ¶ [0048-49] ) . One would have been motivated to include the plurality of bonding pillars because their using in a bonding layer is well-known in the art, as disclosed by Fang, and to have used them to satisfy the additional limitation of claim 9 in order to facilitate the required signal paths. One would have had a reasonable expectation of success because the bonding pillars and associated bonding methods are well-known in the art. Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Park; Heat Bit et al. (US 2018/0374779; hereinafter Park) in view of Oh; Tae-young et al. (US 2011/0309468; hereinafter Oh), and further in view of F ang ; Hsu-Nan ( US 2022 / 0199559 ; hereinafter Fang), and still further in view of Nin; Shu-Liang (US 2012/0267776; hereinafter Nin) . Regarding claim 11 , Park in view of Oh and further in view of Fang discloses the semiconductor device according to claim 9, but does not disclose wherein each of the plurality of semiconductor dies comprises a plurality of top metal interconnection structures . In the same field of endeavor, Nin discloses a similar semiconductor d evice (Figs 2-5; ¶ [0020-33]) comprising a plurality of top metal interconnection structures (404 {404I}; Figs 3-5; ¶ [0021-24]), wherein the plurality of top metal interconnection structures are located on the top surface of the substrate (RDL; ¶ [0021]) . Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the plurality of top metal interconnection structures of Nin with semiconductor device of claim 9, wherein the plurality of top metal interconnection structures are located on the top surface of the substrate, each of the plurality of top metal interconnection structures corresponds to and is electrically connected to a respective one of the plurality of signal via groups, each of the plurality of top metal interconnection structures comprises a plurality of conductive paths (Nin; 500; Fig 2; ¶ [0020]); and comprising 406,408,410; Figs 3,4{unlabeled},5; ¶ [0021-22]) , each of the plurality of conductive paths corresponding to and being electrically connected to a respective one of the plurality of signal vias in the respective one of the plurality of signal via groups (in order to form the spiral signal transmission links explained under claim 8) , and each of the plurality of signal transmission links comprises a respective one of the plurality of signal vias and a respective one of the plurality of conductive paths in each of the plurality of semiconductor dies (per the preceding antecedent explanations) ; wherein each of the plurality of top metal interconnection structures comprises a first conductive layer ( Nin; 406; Fig 3; ¶ [0021]) , a second conductive layer (Nin; 410; Fig 3; ¶ [0021]) , and a plurality of connection elements (Nin; 406a I, 406a II, 406a III, 406a IV; Fig 4 {only 404a I, 404b II, 404c III, and 404d IV are labeled}]; ¶ [0024-25]) , wherein the first conductive layer is located on the top surface of the substrate and comprises a plurality of first conductive elements (Nin; 406, including 406a I, 406a II, 406a III, 406a IV; Figs 3,4) spaced apart from each other, the plurality of first conductive elements are arranged in the polygonal shape ( Nin; as shown in Fig 4, and corresponding the square shape of the TSV’s 402; ¶ [0025]) , and each of the plurality of first conductive elements corresponds to and is electrically connected to a respective one of the plurality of signal vias in the respective one of the plurality of signal via groups (Nin; Fig 4; ¶ [0025] ; and Park; for example 421_0 corresponds to one via/path ; ¶ [0069]) ); wherein the second conductive layer is located on the first conductive layer and comprises a plurality of second conductive elements (unlabeled, analogous to 406a I, 406a II, 406a III, 406a IV for the layer 408; Figs 3,4) spaced apart from each other, each of the plurality of second conductive elements corresponds to a respective one of the plurality of first conductive elements, the plurality of second conductive elements are arranged in the polygonal shape, and a portion of each of the plurality of second conductive elements is overlapped with a portion of the respective one of the plurality of first conductive elements (Nin; Figs 3,4; ¶ [0021-25]) ; and wherein each of the plurality of connection elements corresponds to a respective one of the plurality of first conductive elements and a respective one of the plurality of second conductive elements, and each of the plurality of connection elements is configured to electrically connect the respective one of the plurality of first conductive elements with the respective one of the plurality of second conductive elements, to form a respective one of the plurality of conductive paths (Nin; Figs 3,4,5; ¶ [0021-25]) ; and wherein each of the plurality of first conductive elements comprises a first end and a second end (a left end of 406, over a respective 402 {402 I}, and a right end of 406, under a respective 408, respectively, as shown in Fig 3) , the first end being arranged opposite to the second end along an extension direction of said each of the plurality of first conductive elements, and each of the plurality of second conductive elements comprises a third end and a fourth end (a left end of 410, over a respective 408, and a right end, over an adjacent 402 {402 II}, respectively, as shown in Fig 3) , the third end being arranged opposite to the fourth end along an extension direction of said each of the plurality of second conductive elements; wherein the first end of each of the plurality of first conductive elements corresponds to and is electrically connected to the respective one of the plurality of signal vias (as shown in Nin Fig 3 ) ; and wherein for each of the plurality of second conductive elements and the respective one of the plurality of first conductive elements, an end of a respective one of the plurality of connection elements is electrically connected to the third end of said each of the plurality of second conductive elements, and another end of the respective one of the plurality of connection elements is electrically connected to the second end of the respective one of the plurality of first conductive elements (Nin; as shown in Fig 3; ¶ [0021]) . Regarding claim 12 , Park in view of Oh and further in view of Fang and still further in view of Nin discloses the semiconductor device according to claim 11, wherein for the any two adjacent semiconductor dies stacked face-to-face with each other, each pair of the plurality of pairs of bonding pillar groups corresponds to a respective one of the plurality of top metal interconnection structures of each of the any two adjacent semiconductor dies stacked face-to-face with each other, an end of each of the plurality of bonding pillars is electrically connected to the fourth end of a respective one of the plurality of second conductive elements in one of the any two adjacent semiconductor dies stacked face-to-face with each other, and another end of each of the plurality of bonding pillars is electrically connected to the fourth end of a respective one of the plurality of second conductive elements in another one of the any two adjacent semiconductor dies stacked face-to-face with each other. (The Examiner believes this has been explained and/or is obvious from the explanations in the preceding and antecedent claims in combining the combination of references. In addition, the Examiner believes it has been explained in the above that the combination of references includes each element claimed, and one of ordinary skill could have combined them by known methods to yield predicable results: see MPEP 2143.I.A.) Regarding claim 13 , Park in view of Oh and further in view of Fang and still further in view of Nin discloses the semiconductor device according to claim 11, wherein each of the plurality of semiconductor dies further comprises: a plurality of internal circuits (Park; data transmission circuit 421, comprising 421_0 to 421_32; Figs 3,6A; ¶ [0054-58,0067-70]), wherein each of the plurality of internal circuits corresponds to a respective one of the plurality of top metal interconnection structures (Nin; (404 {404I}; Figs 3-5), and each of the plurality of internal circuits is electrically connected to a respective one of the plurality of conductive paths (Nin; 500; Fig 2; ¶ [0020]); and comprising 406,408,410; Figs 3,4{unlabeled},5; and corresponding the analogous path {CH0, for example} shown in Fig 5 of Park {Park; ¶ [0048]}) in the respective one of the plurality of top metal interconnection structures (Park; for example 421_0 corresponds to one via/path; ¶ [0069]); and a plurality of lead-out wires, wherein each of the plurality of lead-out wires corresponds to a respective one of the plurality of internal circuits, an end of each of the plurality of lead-out wires is electrically connected to the respective one of the plurality of internal circuits, and another end of each of the plurality of lead-out wires is only electrically connected to a respective one of the plurality of first conductive elements in the respective one of the plurality of top metal interconnection structures , wherein for each of the N cell structures, one of the plurality of signal transmission links is only electrically connected to one of the plurality of lead-out wires in one of the plurality of semiconductor dies (as indicated in Fig 6A of Park, and being obvious to a person having ordinary skill in the art that a wire must connect in this fashion in order for the circuit and device to function; the combination of elements between Park and Nin being further obvious due to the similarity in the disclosures of Park and Nin). Regarding claim 14 , Park in view of Oh and further in view of Fang and still further in view of Nin discloses the semiconductor device according to claim 1 3, further comprising: an interface circuit, wherein the interface circuit is located in the base plate and is electrically connected to the plurality of pairs of signal transmission link groups, the interface circuit is configured to transmit a plurality of control signals to the plurality of signal transmission link groups, each of the plurality of control signals corresponding to a respective one of the plurality of signal transmission links in the plurality of signal transmission link groups, and each of the plurality of control signals being only led out from one of the plurality of lead-out wires in one of the plurality of semiconductor dies in each of the N cell structures, wherein for each pair of the plurality of pairs of signal via groups in one of the plurality of semiconductor dies, the interface circuit outputs a first control signal to a lead-out wire electrically connected to one of the plurality of signal vias in one of the plurality of signal via groups through a respective one of the plurality of signal transmission links, and transmits a second control signal, which is different from the first control signal, to a lead-out wire electrically connected to one of the plurality of signal vias in another one of the plurality of signal via groups through another respective one of the plurality of signal transmission links (Park; circuits configured to transmit a control signal {¶ [003 0 ]} according to the description {¶ [0039]} associated at least with Fig 3, and as one of ordinary skill in the art would arrive at in accordance with the explanations for the elements in the combination of references in the preceding antecedent claims) . Claims 10 , 16 -18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park; Heat Bit et al. (US 2018/0374779; hereinafter Park) in view of Oh; Tae-young et al. (US 2011/0309468; hereinafter Oh), and further in view of Nin; Shu-Liang (US 2012/0267776; hereinafter Nin) . Regarding claim 10 , Park in view of Oh discloses the semiconductor device according to claim 8, but does not disclose wherein for any two adjacent semiconductor dies stacked back-to-back with each other, each of the plurality of signal vias in one of the any two adjacent semiconductor dies stacked back-to-back with each other corresponds to and directly electrically contacts with a respective one of the plurality of signal vias in another one of the any two adjacent semiconductor dies stacked back-to-back with each other. In the same field of endeavor, Nin discloses a similar semiconductor die (400 {400a }; Figs 2-5; ¶ [0020-33]) comprising a plurality of top metal interconnection structures (404 {404I}; Figs 3-5; ¶ [0021-24]), which form a spiral or helix conductive path (500; Fig 2; ¶ [0020]) similar that that disclosed by Park (Fig 5, as explained under claim 8). Accordingly, it would have been obvious for a person having ordinary skill in the art to have combined the plurality of top metal interconnection structures of Nin with the disclosure of Park in view of Oh as applied to claim 8. One would have been motivated to do this as a means of connection to implement the spiral shaped connection disclosed by Park (as applied to claim 8) , since Park does not make details of this clear. One would have had a reasonable expectation of success because of the similar structures of both Park and Nin. The resulting implementation of the top metal interconnection structures of Nin with the back-back stacking of two pairs of face-to-face stacked die of Park in view of Oh, results in satisfaction of the further limitations of claim 10 , wherein for any two adjacent semiconductor dies stacked back-to-back with each other, each of the plurality of signal vias in one of the any two adjacent semiconductor dies stacked back-to-back with each other corresponds to and directly electrically contacts with a respective one of the plurality of signal vias in another one of the any two adjacent semiconductor dies stacked back-to-back with each other . (The top metal interconnection structures of Nin are on only one side {the face} of the die, and not on the back-side. It would have been obvious to a person having ordinary skill in the art that the signal vias facing one another back-to-back may then be directly electrically connected, as is known in the art, in respective correspondence to maintain a signal path from one die to another .) Regarding claim 16 , Park in view of Oh discloses the method for forming the semiconductor device according to claim 15, wherein forming the plurality of semiconductor dies comprises: forming the substrate, and defining, in the substrate, the first region arranged on said one side of the axis and the second region arranged on the other side of the axis; forming, in each of the first region and the second region, the plurality of signal via groups penetrating through the substrate along the third direction (an axis obviously exists in the formed substrate about which said first and second regions are formed in order to define the plurality of signal via groups {G0; Fig 4A; as applied to claim 15}). Park in view of Oh does not disclose forming a plurality of top metal interconnection structures on the top surface of the substrate, wherein each of the plurality of top metal interconnection structures corresponds to and is electrically connected to a respective one of the plurality of signal via groups, each of the plurality of top metal interconnection structures comprises a plurality of conductive paths, each of the plurality of conductive paths corresponds to and is electrically connected to a respective one of the plurality of signal vias in the respective one of the plurality of signal via groups. In the same field of endeavor, Nin discloses a similar semiconductor die (400 {400a}; Figs 2-5; ¶ [0020-33]) comprising a plurality of top metal interconnection structures (404 {404I}; Figs 3-5; ¶ [0021-24]) on the top surface of a substrate (400a; Fig 5 , ¶ [0020]), which form a spiral or helix conductive path (500; Fig 2; ¶ [0020]) similar that that disclosed by Park ( CH0, for example; ¶ [0048] ). Accordingly, it would have been obvious for a person having ordinary skill in the art to have combined the plurality of top metal interconnection structures of Nin with the method of Park in view of Oh as applied to claim 15 , wherein each of the plurality of top metal interconnection structures corresponds to and is electrically connected to a respective one of the plurality of signal via groups, each of the plurality of top metal interconnection structures comprises a plurality of conductive paths, each of the plurality of conductive paths corresponds to and is electrically connected to a respective one of the plurality of signal vias in the respective one of the plurality of signal via groups. One would have been motivated to do this as a means of connection to implement the spiral shaped connection as disclosed by Park, since Park does not make details of this clear. One would have had a reasonable expectation of success because of the similar structures of both Park and Nin , and because formation methods are well-known in the art. Regarding claim 17 , Park in view of Oh and further in view of Nin discloses the method for forming the semiconductor device according to claim 16, wherein forming the plurality of top metal interconnection structures on the top surface of the substrate comprises: forming a first conductive layer (Nin; 406; Fig 3; ¶ [0021]) on the top surface of the substrate, wherein the first conductive layer comprises a plurality of first conductive elements (Nin; 406a I, 406a II, 406a III, 406a IV; Fig 4 {only 404a I, 404b II, 404c III, and 404d IV are labeled}]; ¶ [0024-25]) spaced apart from each other, the plurality of first conductive elements are arranged in the polygonal shape (Nin; as shown in Fig 4, and corresponding the square shape of the TSV’s 402; ¶ [0025]) , each of the plurality of first conductive elements comprises a first end and a second end, the first end is arranged opposite to the second end along an extension direction of said each of the plurality of first conductive elements, and the first end of each of the plurality of first conductive elements corresponds to and is electrically connected to a respective one of the plurality of signal vias in a respective one of the plurality of signal via groups (Nin; ¶ [0025]) ; forming a second conductive layer (Nin; 410; Fig 3; ¶ [0021]) above the first conductive layer, wherein the second conductive layer comprises a plurality of second conductive elements (unlabeled, analogous to 406a I, 406a II, 406a III, 406a IV for the layer 408; Figs 3,4) spaced apart from each other, each of the plurality of second conductive elements corresponds to a respective one of the plurality of first conductive elements, the plurality of second conductive elements are arranged in the polygonal shape, each of the plurality of second conductive elements comprises a third end and a fourth end, the third end being arranged opposite to the fourth end along an extension direction of said each of the plurality of second conductive elements, and a portion of each of the plurality of second conductive elements is overlapped with a portion of the respective one of the plurality of first conductive elements (Nin; Figs 3,4; ¶ [0021-25]) ; and forming a plurality of connection elements (Nin; 408; Fig 3; ¶ [0021]) between the first conductive layer and the second conductive layer, wherein for each of the plurality of second conductive elements and the respective one of the plurality of first conductive elements, an end of a respective one of the plurality of connection elements is electrically connected to the third end of said each of the plurality of second conductive elements, and another end of the respective one of the plurality of connection elements is electrically connected to the second end of the respective one of the plurality of first conductive elements, to form a respective one of the plurality of conductive paths (Nin; Figs 3,4,5; ¶ [0021-25]) . Regarding claim 18 , Park in view of Oh and further in view of Nin discloses the method for forming the semiconductor device according to claim 17, wherein forming the stack structure on the base plate based (Park ; 21; Fig 2); on the plurality of semiconductor dies comprises: providing the four semiconductor dies (Park ; 2 2,{31-34} ; Fig s 2 ,{3} ; ¶ [003 4 ]); placing the first semiconductor die on the base plate (Park ; Fig s 2 ,3 ); stacking the second semiconductor die above the first semiconductor die in a manner that the second semiconductor die is arranged face-to-face with the first semiconductor die (as applied to the antecedent claims); stacking the third semiconductor die above the second semiconductor die in a manner that the third semiconductor die is arranged back-to-back with the second semiconductor die (as applied to the antecedent claims) ; stacking the fourth semiconductor die above the third semiconductor die in a manner that the fourth semiconductor die is arranged face-to-face with the third semiconductor die (as applied to the antecedent claims), to form a cell structure comprising the first semiconductor die, the second semiconductor die, the third semiconductor die and the fourth semiconductor die (as applied to the antecedent clai