DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/06/2023 and 06/25/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species A1, B1, C1, D1, and E1 (claims 1-7 and 9-20) in the reply filed on 07/16/2026 is acknowledged.
Claim 8 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/16/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a width of the active pattern in the second direction being greater than that of the bit line, must be shown or the feature canceled from the claim (directional reference in figure is not consistent with claim 9, see specification paragraph 0069). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 10 and 12-16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US Publication 20220102352).
Regarding independent claim 10, Lee teaches a semiconductor memory device (fig. 1), comprising:
bit lines (fig. 4A, BL) extending in a first direction (D1);
active patterns (CP) arranged in the first direction on each of the bit lines, each of the active patterns including a horizontal portion (fig. 5A, HP) parallel to the bit line and vertical portions (VP1 and VP2) vertically protruding from the horizontal portion;
word lines (WL1 and WL2) crossing the bit lines and extending in a second direction (fig. 4A, D2), each of the word lines being on the active patterns arranged in the second direction (fig. 4A);
first electrode patterns connected to the vertical portions of the active patterns, respectively (paragraph 0098, “the bottom electrode may be in contact with the landing pad LP” which connects to the vertical portions, see also fig. 5A);
second electrode patterns on rows of the first electrode patterns arranged in the second direction, each of the second electrode patterns extending in the second direction and parallel to the word lines (paragraph 0098, top electrode);
and a dielectric pattern between the first electrode patterns and each of the second electrode patterns (paragraph 0098, “a capacitor dielectric layer interposed therebetween”).
Regarding dependent claim 12, Lee teaches the semiconductor memory device as claimed in claim 10, wherein the active patterns includes polysilicon or metal oxide (paragraph 0080).
Regarding dependent claim 13, Lee teaches the semiconductor memory device as claimed in claim 10, further comprising landing pads (fig. 4B, LP) between the first electrode patterns and the vertical portions, respectively (first electrode patterns located at bottom of DSP).
Regarding dependent claim 14, Lee teaches the semiconductor memory device as claimed in claim 13, wherein the first electrode patterns penetrate a mold insulating layer (fig. 17C, ML2) to be connected to the landing pads, respectively.
Regarding dependent claim 15, Lee teaches the semiconductor memory device as claimed in claim 10, further comprising shielding lines (fig. 8A, SL1) extending in the first direction between the bit lines adjacent to each other in the second direction (paragraph 0106).
Regarding dependent claim 16, Lee teaches the semiconductor memory device as claimed in claim 10, wherein each of the first electrode patterns (fig. 17C, PE) includes a bottom portion (see figure below) connected to a respective one of the vertical portions (connected via LP2) and a sidewall portion (see figure below) extending
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from the bottom portion.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 11, and 17-20 rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jeon (US Publication 20210202508).
Regarding independent claim 1, Lee teaches a semiconductor memory device (fig. 1), comprising:
a bit line (fig. 4A, BL) extending in a first direction (D1);
an active pattern (CP) on the bit line, the active pattern including first and second vertical portions (fig. 5A, VP1 and VP2) facing each other in the first direction and a horizontal portion (HP) connecting the first and second vertical portions;
first and second word lines (WL1 and WL2) on the horizontal portion between the first and second vertical portions, the first and second word lines extending in a second direction (fig. 4A, D2) crossing the first direction;
a gate insulating pattern (Gox) between the first and second word lines and the active pattern; and
a capacitor (DSP) connected to each of the first and second vertical portions (paragraph 0097), the capacitor including:
a first electrode pattern connected to one of the first and second vertical portions (paragraph 0098, “the bottom electrode may be in contact with the landing pad LP” which connects to the vertical portions, see also fig. 5A),
a second electrode pattern on the first electrode pattern (paragraph 0098, top electrode).
Lee does not teach and a ferroelectric pattern between the first electrode pattern and the second electrode pattern.
Jeon teaches and a ferroelectric pattern (fig. 1, 13) between the first electrode pattern (11) and the second electrode pattern (15).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor memory device of Lee and the ferroelectric pattern of Jeon to generate oxygen vacancies (Jeon paragraph 0016).
Regarding dependent claim 2, Lee further teaches the semiconductor memory device as claimed in claim 1, wherein the first electrode pattern (fig. 17C, PE) includes a bottom portion connected to the one of the first and second vertical portions (connected via LP2) and a side wall portion extending from the bottom portion (see marked figure corresponding to claim 16).
Regarding dependent claim 3, Lee further teaches the semiconductor memory device as claimed in claim 2, wherein the second electrode pattern includes:
a line portion extending in the second direction (fig. 17C); and
a filler portion filling a space defined by the bottom portion and the side wall portion of the first electrode pattern (fig. 17C).
Regarding dependent claim 4, Lee further teaches the semiconductor memory device as claimed in claim 2, wherein the ferroelectric pattern covers the bottom portion and the side wall portion of the first electrode pattern with a uniform thickness (fig. 17C, CIL corresponds to ferroelectric pattern of Jeon).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor memory device of Lee and the ferroelectric pattern material of Jeon per the reason(s) stated above in claim 1.
Regarding dependent claim 5, Jeon further teaches the semiconductor memory device as claimed in claim 1, wherein the ferroelectric pattern includes HfO2, HfSiO2, HfAlO2, HfSiON, HfZnO, HfZrO2, ZrO2, ZrSiO2, HfZrSiO2, ZrSiON, LaAlO, HfDyO2, or HfScO2 (paragraph 0012, “may include hafnium zirconium oxide (HZO), hafnium titanium oxide, or hafnium silicon oxide”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor memory device of Lee and the ferroelectric pattern material of Jeon per the reason(s) stated above in claim 1.
Regarding dependent claim 6, Lee further teaches the semiconductor memory device as claimed in claim 1, wherein the active pattern includes polysilicon or metal oxide (paragraph 0080).
Regarding dependent claim 7, Lee further teaches the semiconductor memory device as claimed in claim 1, further comprising a landing pad (fig. 5A, LP) between the first electrode pattern and one of the first and second vertical portions.
Lee does not explicitly teach a bottom surface of the landing pad being at a level lower than an upper surface of the gate insulating pattern.
Regarding dependent claim 9, Lee further teaches the semiconductor memory device as claimed in claim 1, wherein: the bit line has a first width (fig. 4A, W1) in the second direction, and the active pattern has a second width (W2) greater than the first width in the second direction.
Regarding dependent claim 11, Lee teaches the semiconductor memory device as claimed in claim 10.
Lee does not teach wherein the dielectric pattern includes a ferroelectric material, an antiferroelectric material, a paraelectric material, or a combination thereof.
Jeon teaches wherein the dielectric pattern (fig. 1, 13) includes a ferroelectric material, an antiferroelectric material, a paraelectric material, or a combination thereof (paragraph 0075).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor memory device of Lee and the ferroelectric pattern of Jeon to generate oxygen vacancies (Jeon paragraph 0016).
Regarding independent claim 17, Lee teaches a semiconductor memory device (fig. 2), comprising:
a semiconductor substrate (100);
a peripheral circuit structure (PS) including peripheral circuits (fig. 4B, SA) on the semiconductor substrate and a lower insulating layer (110) covering the peripheral circuits (paragraph 0066);
bit lines (fig. 4A, BL) extending in a first direction (D1) on the peripheral circuit structure;
active patterns (CP) arranged in the first direction on each of the bit lines, each of the active patterns including a horizontal portion (fig. 5A, HP) parallel to the bit line and vertical portion (VP1 and VP2) vertically protruding from the horizontal portion;
word lines (fig. 4B, WL1 and WL2) crossing the bit lines and extending in a second direction (fig. 4A, D2), each of the word lines being on the active patterns arranged in the second direction (fig. 4B);
first electrode patterns (fig. 17C, PE) connected to the vertical portions of the active patterns (connected via LP, see also paragraph 0167), each of the first electrode patterns including a bottom portion connected to a respective one of the vertical portions (fig. 17C, connected via LP) and a side wall portion extending from the bottom portion (fig. 17C);
second electrode patterns (BE) on rows of the first electrode patterns arranged in the second direction, each of the second electrode patterns including a line portion extending in the second direction and a filler portion filling a space defined by the bottom portion and the side wall portion of the first electrode pattern (fig. 17C).
Lee does not teach and a ferroelectric pattern between the first electrode patterns and each of the second electrode patterns.
Jeon teaches and a ferroelectric pattern (fig. 1, 13) between the first electrode pattern (11) and the second electrode pattern (15).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor memory device of Lee and the ferroelectric pattern of Jeon to generate oxygen vacancies (Jeon paragraph 0016).
Regarding dependent claim 18, Lee further teaches the semiconductor memory device as claimed in claim 17, further comprising landing pads (fig. 17C, LP2) between the first electrode patterns and the vertical portions of the active patterns, respectively.
Regarding dependent claim 19, Lee further teaches the semiconductor memory device as claimed in claim 17, wherein the vertical portions include first (fig. 5A, VP1) and second vertical portions (VP2) on each of the active patterns, the first and second vertical portions facing each other in the first direction and are commonly connected to the horizontal portion (fig. 5A).
Regarding dependent claim 20, Lee further teaches the semiconductor memory device as claimed in claim 17, further comprising first insulating patterns (fig. 4A, 115) extending in the second direction across the bit lines, each of the first insulating patterns being between the active patterns adjacent to each other in the first direction (fig. 4A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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