DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/23/2026 has been entered.
This communication is responsive to the request for continued examination filed on 4/23/2026. Claims 1-9, 11-20 and 22-25 are pending and have been examined. Claims 1, 17-18 and 22-23 have been amended. Claims 24-25 have been added. Claims 7, 10 and 21 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8, 11, 14, 16-19 and 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over, Spasov, PGPUB No. 2018/0107487, Sodani, PGPUB No. 2008/0148282 and further in view of Slavenburg, USPAT No. 5,832,202.
In regards to claim 1, Spasov discloses A processor-implemented method for instruction execution ([0006-0007 and Fig. 1]) comprising: accessing a processor core, and wherein the processor core executes one or more instructions out of order ([0015-0016 and 0019-0020]: wherein a processor core is accessed and the processor core includes execution units that execute instructions issued in any order, and are thus executed out-of-order (See Fig. 1)) maintaining an ordered list of instructions, wherein the ordered list is based on instructions that are presented to the processor core for execution ([0018-0021]: wherein a reorder buffer maintains an ordered list of instructions, wherein the ordered list of instructions is based on instructions that are presented to the processor core (element 100)) and wherein the ordered list is organized using one or more pointers ([0019-0020]: wherein the reorder buffer is organized using tail and head pointers (Figs. 1-2B)) detecting an execution exception in the processor core, wherein the execution exception corresponds to one of the instructions in the ordered list ([0020-0022]: wherein an execution exception is detected in execution unit (element 110). Wherein the execution exception corresponds to one of the instructions in the reorder buffer)
and wherein the execution exception requires initiating exception handling ([0019-0020]: wherein execution exception requires flushing the core (i.e., exception handling)) determining an effective age of an instruction in the ordered list that corresponds to the execution exception ([0019-0022]: wherein an effective age of an instruction that corresponds to the execution exception is determined using index I of instruction in reorder buffer as the index indicates the position of the instruction and the position indicates the age of the instruction relative to other instructions in ROB) initiating the exception handling, based on matching the effective age of an instruction in the ordered list with one of the one or more pointers ([0018-0023 and 0027]: wherein initiating flushing of the core is based on matching (comparing) the effective age indicated by the index of the instruction in the reorder buffer with the tail or head pointer of the reorder buffer (See Figs. 4-5))
wherein the match of the effective age of the instruction in the ordered list is established by comparison to a head pointer ([0022-0027]: wherein the match of the effective age (relative age) of the instruction in the reorder buffer is established by comparing an index of the instruction to a head pointer index (also see [0020-0021] for further clarity)) wherein the accessing, the maintaining, the detecting, and the determining enable delaying the exception handling based on information in the ordered list. (Spasov [0020-0022 and Figs. 3-5]: wherein flushing (exception handling) is delayed until after the accessing, maintaining, detecting and determining have occurred because flushing of instructions does not occur until after those steps. Wherein those steps are based on information in the ordered list)
Spasov does not disclose wherein the processor core executes at least one instruction thread, and wherein the execution exception requires initiating an exception handling routine, wherein the detecting delays initiating the exception handling routine to allow instructions that did not generate the execution exception to complete execution; and initiating the exception handling routine, based on matching the effective age of an instruction in the ordered list nor wherein the detecting and the determining enable delaying the exception handling routine based on information in the ordered list, and without using data stored in a reorder buffer.
Sodani discloses wherein the processor core executes at least one instruction thread ([0027, 0033, 0037 and 0090]: wherein the processor core executes at least one instruction thread) wherein the execution exception requires initiating an exception handling routine ([0015, 0023 and 0077]: wherein execution exception requires invoking exception handler code and flushing instructions) initiating the exception handling routine, based on matching the effective age of an instruction in the ordered list ([0072-0077]: wherein initiating the exception handler code based on matching the effective age indicated by the instruction sequence number of the instruction in the ROB) wherein the detecting and the determining enable delaying the exception handling routine based on information in the ordered list, and without using data stored in a reorder buffer. ([0072-0077]: wherein the exception handling routine (performed at element 612) is delayed, based on a sequence number identifying a candidate instruction for retirement; wherein the sequence number identifies an exception generating instruction in the ordered list of instructions in the ROB (see [0045]) and therefore the delaying of the exception handling routine is based on information in the ordered list of the ROB. Furthermore, the exception handling routine is delayed when the event status register, including the sequence number, indicates that a sticky event is to be recorded at step 613 and then exception handling is to be performed at step 612 (see [0076-0077]). Thus, exception handling routine is delayed based on information (sequence number stored in event status register indexing the ordered list of ROB), and without using data stored in ROB)
It would have first been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor core of Spasov to execute a thread of instructions as the processor core of Sodani. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (executing instructions of a thread using a processor core as taught in Sodani) for another (generically executing instructions using a processor core as taught in Spasov) to obtain predictable results (executing instructions of a thread using a processor core) (MPEP 2143, Example B).
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Spasov which flushes instructions responsive to instruction exception detection to initiate an exception handling routine which flushes instructions responsive to instruction exception detection as taught in Sodani. It would have been obvious to one of ordinary skill in the art because using an exception handling routine to flush instructions allows for software to perform efficient error recovery in a processor (i.e., software exception routines can provide more flexibility and improved reliability). Furthermore, it would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (flushing instructions using exception handling routine initiated responsive to instruction exception as taught in Sodani) for another (generically flushing instructions responsive to instruction exception as taught in Spasov) to obtain predictable results (flushing instruction using exception handling routine initiated responsive to instruction exception) (MPEP 2143, Example B).
Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor core of Spasov to include an event status register to track exception information used for exception handling as the processor core of Sodani. It would have been obvious to one of ordinary skill in the art because using the event tracking register avoids or reduces overhead expense of unnecessarily tracking event status per instruction (Sodani [0026]).
The combination of Spasov and Sodani does not disclose wherein the detecting delays initiating the exception handling routine to allow instructions that did not generate the execution exception to complete execution.
Slavenburg discloses wherein the detecting delays initiating the exception handling routine to allow instructions that did not generate the execution exception to complete execution (Column 4, lines 4-9: wherein exception handling routine is delayed to allow operations that started before the exception to complete execution)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Spasov and Sodani that detects exceptions and initiates exception handling routines to delay initiating exception handling routines to allow instructions prior to the exception to complete instructions as taught in Slavenburg. It would have been obvious to one of ordinary skill in the art because allowing instructions which were executing prior to an exception event to complete before handling the exception can be used to ensure that machine state is correct when normal execution resumes from the point of exception (Slavenburg: Column 4, lines 4-15). Furthermore, it would be obvious because it would allow precise exception handling to occur which simplifies exception handling and provides easier debugging and restarting of program execution.
Claim 22 is similarly rejected on the same basis as claim 1 as claim 22 is the computer program product corresponding to the method of claim 1. (Note: claim 22 includes limitations not stated in claim 1 such as “A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors”. However, Spasov discloses the above limitation in paragraph [0034])
Claim 23 is similarly rejected on the same basis as claim 1 as claim 23 is the computer system corresponding to the method of claim 1. (Note: claim 23 includes limitations not stated in claim 1 such as “A computer system for instruction execution comprising: a memory which stores instructions; one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored”. However, Spasov discloses the above limitation in paragraphs [0016 and 0034] and Fig. 6)
In regards to claim 2, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 1 (see rejection of claim 1 above) wherein the ordered list of instructions is maintained in a circular queue. (Spasov [0018]: wherein ordered list of instructions is maintained in a circular buffer| Sodani [0019])
In regards to claim 3, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 2 (see rejection of claim 2 above) wherein the one or more pointers that are used to organize the ordered list comprise the head pointer and a tail pointer within the circular queue. (Spasov [0018])
In regards to claim 4, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 3 (see rejection of claim 3 above) wherein the tail pointer indicates a youngest, non-retired instruction in the ordered list of instructions. (Spasov [0019 and 0021])
In regards to claim 5, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 3 (see rejection of claim 3 above) wherein the head pointer indicates an oldest, non-retired instruction in the ordered list of instructions. (Spasov [0019 and 0021])
In regards to claim 6, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 5 (see rejection of claim 5 above) wherein the effective age of an instruction corresponds to an address within the circular queue. (Spasov [0019-0022]: wherein effective age (relative age) of an instruction corresponds to a location/position (i.e., an address) indicated by an index within the circular buffer| Sodani [0045])
In regards to claim 8, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 1 (see rejection of claim 1 above) wherein the comparison comprises an "equal to" comparison. (Spasov [0024-0027, 0030]: wherein head pointer index is compared to determine if instruction index is greater than or equal to head pointer (A≥B))
In regards to claim 11, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 1 (see rejection of claim 1 above) further comprising coupling a register in the processor core for storing an index related to the ordered list. (Sodani [0026 and 0045]: wherein an event tracker register coupled in the processor stores a sequence number value (index) into reorder buffer (See Fig. 3))
In regards to claim 14, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 11 (see rejection of claim 11 above) wherein the index comprises an address of an entry in the ordered list. (Sodani [0045]: wherein the sequence number value comprises an address or location of an entry in the ROB)
In regards to claim 16, the combination of Spasov, Sodani and Slavenburg thus far discloses The method of claim 1 (see rejection of claim 1 above).
The combination of Spasov, Sodani and Slavenburg thus far does not explicitly disclose wherein the execution exception is related to a fetch or a decode exception. Spasov generally discloses an execution exception but does not explicitly disclose the cause of the exception or what type of exception occurred.
Sodani discloses wherein the execution exception is related to a fetch or a decode exception. ([0043]: wherein the execution exception is related to a fetch exception (page access fault, data segment fault, etc.))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the execution exception of Spasov to be related to a fetch or decode exception as in Sodani. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (fetch or decode exception as taught in Sodani) for another (generic exception as taught in Spasov) to obtain predictable results (detecting and handling fetch and decode exceptions in a processor) (MPEP 2143, Example B).
In regards to claim 17, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 16 (see rejection of claim 16 above).
The combination of Spasov, Sodani and Slavenburg thus far does not disclose wherein the fetch or the decode exception comprises an address translation fault, an alignment fault, or an illegal opcode. Sodani discloses various faults and exceptions such as page faults, code segment faults and so forth.
Slavenburg discloses wherein the fetch or the decode exception comprises an address translation fault, an alignment fault, or an illegal opcode (abstract and column 1, lines 60-67: wherein a page fault (address translation fault) and traps to emulate un-implemented opcodes (illegal opcodes) is disclosed)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the exceptions of Spasov and Sodani to include address translation faults and illegal opcode exceptions as taught in Slavenburg. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (a page fault or illegal opcode exception as taught in Slavenburg) for another (various exceptions of Sodani) to yield predictable results (initiating an exception handling routine in light of a page fault or illegal opcode) (MPEP 2143, Example B).
In regards to claim 18, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 16 (see rejection of claim 16 above). wherein the detecting an execution exception in the processor core prevents execution of any new instructions not already in the ordered list of instructions (Spasov [0020-0027]: wherein responsive to detecting exception in the processor core the pipeline is flushed as to remove any instructions younger than the exception instruction, whereas older instructions are maintained and allowed to execute. Thus, exception detection prevents any new or younger instructions not already in the reorder buffer from executing |Sodani [0023-0025, 0054 and 0077]) wherein the preventing execution of any new instructions occurs while the exception handling routine is executing. (Sodani [0023-0025, 0054 and 0077]: wherein a part of executing the exception handling routine involves flushing younger instructions and executing the exception routine and thus execution of new instructions is prevented while the exception handling routine is executing (e.g. the routine is the only code executing at that point in time))
In regards to claim 19, the combination of Spasov, Sodani and Slavenburg thus far discloses The method of claim 1 (see rejection of claim 1 above).
The combination of Spasov, Sodani and Slavenburg thus far does not explicitly disclose wherein the execution exception is related to a breakpoint or watchpoint. Spasov generally discloses an execution exception but does not explicitly disclose the cause of the exception or what type of exception occurred.
Sodani discloses wherein the execution exception is related to a breakpoint or watchpoint. ([0017 and 0043]: wherein the execution exception is related to a breakpoint because it causes breakpoint processing)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the execution exception of Spasov to be related to a breakpoint as the exception in Sodani. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (exception related to breakpoint processing as taught in Sodani) for another (generic exception as taught in Spasov) to obtain predictable results (detecting and handling exceptions related to breakpoints in a processor) (MPEP 2143, Example B).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over, Spasov, Sodani, Slavenburg and further in view of Tran, USPAT No. 5,887,152.
In regards to claim 9, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 1 (see rejection of claim 1 above) wherein the comparison comprises comparing a position value corresponding to the instruction with a position value corresponding the oldest, non-retired instruction in the ordered list of instructions. (Spasov [0024-0027 and 0030]: wherein head pointer index (position of oldest instruction in ROB) is compared to determine instruction index (position value corresponding to instruction in ROB) is greater than or equal to head pointer (A≥B))
The combination of Spasov, Sodani and Slavenburg does not disclose a comparison with a position value corresponding to a value of one less than the oldest, non-retired instruction in the ordered list of instructions.
Tran discloses a comparison with a position value corresponding to a value of one less than the oldest, non-retired instruction in the ordered list of instructions. (Column 10, lines 36-67: wherein a second oldest pointer of a reorder buffer is compared)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the comparisons using the ROB of Spasov to compare a value to a second oldest instruction of an ROB as taught in Tran. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (comparing an index position to a second oldest instruction in an ROB as taught in Tran) for another (comparing an index position to an oldest instruction in ROB in Spasov) to obtain predictable results (comparing an index position of an instruction in a ROB to a second oldest instruction position in an ROB) (MPEP 2143, Example B). Furthermore, the comparison can be used as a mechanism for branch recovery and a mechanism for performing load data cache misses and store ordering (Tran: Column 10, line 65-67 to Column 11, line 1).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over, Spasov, Sodani, Slavenburg and further in view of Tamai, PGPUB No. 2007/0028077.
In regards to claim 12, the combination of Spasov, Sodani and Slavenburg discloses The method of claim 11 (see rejection of claim 11 above).
The combination of Spasov, Sodani and Slavenburg does not disclose wherein entries in the ordered list each comprise a plurality of instruction execution fields. While Spasov and Sodani disclose a reorder buffer including a plurality of entries for instructions and instruction information. Neither reference explicitly discloses a reorder buffer entry comprising a plurality of execution fields.
Tamai discloses wherein entries in the ordered list each comprise a plurality of instruction execution fields. (See Fig. 8 and [0105-0115]: wherein entries of the reorder buffer comprise a plurality of fields)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the reorder buffer entries of Spasov to include a plurality of instruction execution fields as the reorder buffer in Tamai. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (including instruction execution fields in entries of a reorder buffer as taught in Tamai) for another (generic reorder buffer entries as taught in Spasov) to obtain predictable results (using a reorder buffer with entries comprising a plurality of instruction execution fields) (MPEP 2143, Example B).
In regards to claim 13, the combination of Spasov, Sodani, Slavenburg and Tamai discloses The method of claim 12 (see rejection of claim 12 above). wherein the effective age of an entry in the ordered list is independent of all of the plurality of instruction execution fields. (Spasov [0021]: wherein age of an entry is based on position or location of entry in the ROB and independent of data in the entry| Tamai: See Fig. 8 and [0105-0115]: wherein the age of an entry in a reorder buffer is based on position or location of entry in the ROB and independent of data in the entry fields (note: the combination of references would teach the above limitation))
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over, Spasov, Sodani, Slavenburg and further in view of Hocken, USPAT No. 6,286,346.
In regards to claim 15, the overall combination of Spasov, Sodani and Slavenburg discloses The method of claim 11 (see rejection of claim 11 above).
The overall combination of Spasov, Sodani and Slavenburg does not disclose wherein the register comprises an eight-bit register. Sodani discloses the register storing an index but does not indicate the size of the register.
Hocken discloses eight-bit registers (See Fig. 6, elements 238-240).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the register of Sodani to be an eight-bit register as in Hocken. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using an eight-bit register to store data as taught in Hocken) for another (generic register to store an index as taught in Sodani) to obtain predictable results (using an eight-bit register to store an index) (MPEP 2143, Example B). Furthermore, it would have been obvious because changes in size (using a register with a different size/width) have been deemed obvious by the courts (See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (MPEP 2144.04IV(A))).
Claim(s) 20 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over, Spasov, Sodani, Slavenburg and further in view of Ramirez, PGPUB No. 2014/0101412.
In regards to claim 20, the combination of Spasov, Sodani and Slavenburg thus far discloses The method of claim 1 (see rejection of claim 1 above).
The combination of Spasov, Sodani and Slavenburg thus far does not explicitly disclose wherein the exception handling routine changes privilege levels in the processor core. Sodani generally discloses an exception handling routine but does not explicitly disclose the routine changes a privilege level.
Ramirez discloses wherein the exception handling routine changes privilege levels in a processor. ([0020 and 0024]: wherein the exception handling routine changes privilege level in a processor (See Figs. 1-2))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the exception handling routine of Spasov and Sodani to change a privilege level as the exception routine in Ramirez. It would have been obvious to one of ordinary skill in the art because changing a privilege level when an exception associated with a lower privilege level is encountered will prevent access from code in the lower privilege level from accessing more secure code (kernel level privileged code), thus avoiding inappropriate access of secure applications by less secure applications.
In regards to claim 24, the combination of Spasov, Sodani, Slavenburg and Ramirez discloses The method of claim 20 (see rejection of claim 20 above) wherein the changing privileges levels in the processor core is used to suspend instructions, halt execution of instructions (Ramirez [0023-0026]: wherein changing privilege levels to kernel mode suspends and halts execution of user mode instruction stream (e.g. instructions D,E and F) until privilege level is returned to user mode (See Figs. 2-3)) and delete instructions. (Ramirez [0033-0035]: wherein elevating (changing) privilege levels speculatively causes instructions to be flushed (deleted))
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over, Spasov, Sodani, Slavenburg and further in view of Greenhalgh, PGPUB No. 2021/0294642.
In regards to claim 25, the combination of Spasov, Sodani, Slavenburg discloses The method of claim 1 (see rejection of claim 1 above).
The combination of Spasov, Sodani and Slavenburg does not explicitly disclose wherein recovery from the execution exception includes retiring instructions from the ordered list of instructions. Spasov and Sodani disclose using a reorder buffer to store an ordered list of instructions, and in response to execution exception younger instructions are flushed in order to perform precise exception handling. One of ordinary skill in the art would know that instructions older than the exception are committed, however the references do not explicitly state such. Thus, the examiner brings in an additional reference for an explicit teaching.
Greenhalgh discloses wherein recovery from the execution exception includes retiring instructions from the ordered list of instructions ([0095-0096]: wherein the reorder buffer is drained during recovery by committing (retiring) instructions that completed prior to an interrupt occurring)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the recovery of exceptions in Spasov and Sodani to include retiring instructions that completed before the exception point as taught in Greenhalgh. It would have been obvious to one of ordinary skill in the art because it guarantees all instructions preceding the interrupt are executed and committed, allowing the system to resume accurately after the interrupt has been serviced.
Response to Arguments
Applicant’s arguments, see pages 7-10 of remarks, filed on 4/23/2026, with respect to the rejection(s) of claim(s) 1 and 22-23 under 35 USC 103 in view of Spasov and Sodani have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 USC 103 in view of Spasov, Sodani and Slavenburg.
The dependent claims are argued at least based upon their dependency to independent claim 1 and thus remain rejected at least based upon dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183
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