DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/23/2025 was filed after the mailing date of the specification on 12/6/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 8-16, & 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20230369218 A1 to Li et al. (hereinafter “Li”).
Regarding claim 1, Li teaches a semiconductor device (fig. 14C) comprising:
stacked transistors (FETs 114 and 116; fig. 9A) [0045] comprising a bottom transistor (FET 114; fig. 9A) [0045] below (vertically toward back-side) a top transistor (FET 116; fig. 9A) [0045], the bottom transistor (116) comprising a first bottom source/drain region (S/D 118c; fig. 9C) [0043] and a second bottom source/drain region (S/D 118b; fig. 9C) [0043];
a first backside contact (contact 170c; fig. 9C) [0056] connected to the first bottom source/drain region (118c) and a frontside wiring (BOEL metal levels 160; fig. 9C) [0051];
a second backside contact (contact 170a; fig. 9C) [0055] connected to the second bottom source/drain region (118b) and a backside power plane (plane of power level 188; fig. 9C) [0056]; and
a connection via (contact 110b and contact 170b with power wire 184b directly in contact with 188; fig. 9C) [0050] & [0056] formed through (at least being disposed at one end of) the backside power plane (188) to connect a top source/drain region (S/D 122b; fig. 9C) [0044] of the top transistor (116) to a backside power rail (structure of power level 188; fig. 9C) [0056].
To further clarify, regarding the term “formed through,” it is interpreted that the broadest reasonable interpretation of this term includes at least being disposed in contact with one end of. The Examiner notes that this interpretation seems to be broader than what the Applicant may intend in light of the as-filed specification, but when the term is given its plain meaning, the interpretation above is within the skill of an ordinary person in the art to contemplate. It is suggested to amend the above claim to modify the above phrase as “advancing through each vertical boundary of,” at least evidenced by fig. 14C of the as-filed specification to bring the interpretation of the connection via more in-line with the assumed intent of this element in light of the as-filed specification.
Regarding claim 2, Li teaches the semiconductor device of claim 1, wherein a dielectric cap (dielectric isolation 136 on 118c; fig. 9C) [0046] is formed under the first backside contact (170c), the dielectric cap (136) isolating the first backside contact (118c) from the backside power plane (188).
Regarding claim 3, Li teaches the semiconductor device of claim 2, wherein the first backside contact (170c) and the second backside contact (170a) are formed through a portion of a backside interlayer dielectric (ILD) layer (182; fig. 9C) [0056], the backside ILD layer (182) being different (structurally different) from the dielectric cap (136).
Regarding claim 4, Li teaches the semiconductor device of claim 2, wherein the connection via (110b) is formed through (vertically advancing through) the dielectric cap (136) and the second backside contact (170a).
Regarding claim 5, Li teaches the semiconductor device of claim 1, wherein the first (170c) and second (170a) backside contacts comprise a top dimension (dimension of side closest to front side 106b) and a bottom dimension (dimension of side closest to back side 106c), the bottom dimension (side of 106c) being greater than the top dimension (side of 106b).
Regarding claim 6, Li teaches the semiconductor device of claim 1, wherein a deep through via (110a; fig. 9C) [0048] connects the first backside contact (170c) to the frontside wiring (160).
Regarding claim 7, Li teaches the semiconductor device of claim 1, wherein a deep through via 112b) connects the connection via (110b) to the top source/drain region (122b) of the top transistor (116).
Regarding claim 9, Li teaches the semiconductor device of claim 1, wherein the connection via has sidewalls (material laterally flanking 110b) formed of a dielectric material (ILD 144; fig. 9C) [0047].
Regarding claim 10, Li teaches a method comprising:
providing stacked transistors (FETs 114 and 116; fig. 9A) [0045] comprising a bottom transistor (FET 114; fig. 9A) [0045] below (vertically toward back-side) a top transistor (FET 116; fig. 9A) [0045], the bottom transistor (114) comprising a first bottom source/drain region (S/D 118c; fig. 9C) [0043] and a second bottom source/drain region (S/D 118b; fig. 9C) [0043];
forming a first backside contact (contact 170c; fig. 9C) [0056] connected to the first bottom source/drain region (118c) and a frontside wiring (BOEL metal levels 160; fig. 9C) [0051];
forming a second backside contact (contact 170a; fig. 9C) [0055] connected to the second bottom source/drain region (118b) and a backside power plane (plane of power level 188; fig. 9C) [0056]; and
forming a connection via (contact 110b and contact 170b with power wire 184b directly in contact with 188; fig. 9C) [0050] & [0056] through (at least being disposed at one end of) the backside power plane (188) to connect a top source/drain region (S/D 122b; fig. 9C) [0044] of the top transistor (116) to a backside power rail (structure of power level 188; fig. 9C) [0056].
To further clarify, regarding the term “through,” it is interpreted that the broadest reasonable interpretation of this term includes at least being disposed in contact with one end of. The Examiner notes that this interpretation seems to be broader than what the Applicant may intend in light of the as-filed specification, but when the term is given its plain meaning, the interpretation above is within the skill of an ordinary person in the art to contemplate. It is suggested to amend the above claim to modify the above phrase as “advancing through each vertical boundary of,” at least evidenced by fig. 14C of the as-filed specification to bring the interpretation of the connection via more in-line with the assumed intent of this element in light of the as-filed specification.
Regarding claim 11, Li teaches the method of claim 10, wherein a dielectric cap (136) is formed under (at least partially covering) the first backside contact (170c), the dielectric cap (136) isolating the first backside contact (170c) from the backside power plane (188).
Regarding claim 12, Li teaches the method of claim 11, wherein the first backside contact (170c) and the second backside contact (170a) are formed through a portion of a backside interlayer dielectric (ILD) layer (182; fig. 9C) [0056], the backside ILD layer (182) being different (structurally different) from the dielectric cap (136).
Regarding claim 13, Li teaches the method of claim 11, wherein the connection via (110b) is formed through (vertically passing through) the dielectric cap (136) and the second backside contact (170a0.
Regarding claim 14, Li teaches the method of claim 10, wherein the first (170c) and second (170a) backside contacts comprise a top dimension (dimension of side closest to front side 106b) and a bottom dimension (dimension of side closest to back side 106c), the bottom dimension (side of 106c) being greater than the top dimension (side of 106b).
Regarding claim 15, Li teaches the method of claim 10, wherein a deep through via (110a; fig. 9C) [0048] connects the first backside contact (170c) to the frontside wiring (160).
Regarding claim 16, Li teaches the method of claim 10, wherein a deep through via 112b) connects the connection via (110b) to the top source/drain region (122b) of the top transistor (116).
Regarding claim 18, Li teaches the method of claim 10, wherein the connection via has sidewalls (material laterally flanking 110b) formed of a dielectric material (ILD 144; fig. 9C) [0047].
Regarding claim 19, Li teaches a method comprising:
providing a first backside contact (contact 170c; fig. 9C) [0056] connected to a first source/drain region (S/D 118c; fig. 9C) [0043] of a first transistor (bottom FET 114; fig. 9C) [0043] and a frontside wiring (BOEL metal levels 160; fig. 9C) [0051];
providing a second backside contact (contact 170a; fig. 9C) [0055] connected to another first source/drain region (S/D 118b; fig. 9C) [0043] of the first transistor (114) and a backside power plane (plane of additional power level 188; fig. 9C) [0056]; and
providing a connection via (contact 110b and contact 170b with power wire 184b directly in contact with 188; fig. 9C) [0050] & [0056] formed through (at least being disposed at one end of) the backside power plane (188) to connect a second source/drain region (S/D 122b; fig. 9C) [0044] of a second transistor (upper FET 116; fig. 9A) [0043] to a backside power rail (structure of power level 188; fig. 9C) [0056], the second transistor (116) being stacked (see fig. 9A) on the first transistor (114).
To further clarify, regarding the term “through,” it is interpreted that the broadest reasonable interpretation of this term includes at least being disposed in contact with one end of. The Examiner notes that this interpretation seems to be broader than what the Applicant may intend in light of the as-filed specification, but when the term is given its plain meaning, the interpretation above is within the skill of an ordinary person in the art to contemplate. It is suggested to amend the above claim to modify the above phrase as “advancing through each vertical boundary of,” at least evidenced by fig. 14C of the as-filed specification to bring the interpretation of the connection via more in-line with the assumed intent of this element in light of the as-filed specification.
Regarding claim 20, Lit teaches the method of claim 19, wherein a dielectric cap (MDI 136; fig. 9C) [0046] is formed under the first backside contact (170c), the dielectric cap (136) isolating the first backside contact (170c) from the backside power plane (plane of 188).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of U.S. Pat. Pub. No. US 20230197612 A1, which is of record, to Majhi et al. (hereinafter “Majhi”).
Regarding claim 8, Li does not teach the semiconductor device of claim 1, wherein the backside power plane connects to another backside power rail different from the backside power rail.
Majhi, however, teaches a semiconductor device (fig. 2) wherein the backside power plane (plane of 142; fig. 2) [0039] connects to another backside power rail (see below, connecting to bump 182b) different from the backside power rail (see below, connecting to bump 182a).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the device of Li to comprise another backside power rail to allow for the supply of power through an attached bump as taught by Majhi [0054].
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Fig. 2 from Majhi
Regarding claim 17, Li does not teach the method of claim 10, wherein the backside power plane connects to another backside power rail different from the backside power rail.
Majhi, however, teaches a semiconductor device (fig. 2) wherein the backside power plane (plane of 142; fig. 2) [0039] connects to another backside power rail (see below, connecting to bump 182b) different from the backside power rail (see below, connecting to bump 182a).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the device of Li to comprise another backside power rail to allow for the supply of power through an attached bump as taught by Majhi [0054].
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Fig. 2 from Majhi
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Pat. Pub. No. US 20230187551 A1 to Cheng et al. teaches a stacked transistor structure with backside and frontside contacts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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