Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-6, 8 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PARK (Pub. No.: US 2020/0402579) filed in the IDS on 12/06/2023.
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Re claim 2, PARK, FIG. 30 [as shown above] teaches a semiconductor memory device comprising:
a substrate (2210);
a transistor (2220) provided above the substrate; a plurality of bit lines provided above the transistor, each extending in a first direction (horizontal), and arranged in a second direction (vertical) intersecting the first direction, the plurality of bit lines including a first bit line (2271c);
a contact plug (2230/2240) provided below the first bit line, in contact with the first bit line and extending in a third direction perpendicular to the first direction and the second direction;
a plurality of first conductive layers (2350/2350) provided above the first bit line and stacked in the third direction; and
a pillar (CH) including a semiconductor layer penetrating the plurality of first conductive layers in the third direction and electrically connected to the first bit line, wherein
the first bit line (2271c) includes a first portion [FP] that overlaps the contact plug in the third direction (horizontal line at different location) and a second portion [SP] other than the first portion, and
a thickness of the first portion [FP] in the third direction (horizontal) is thinner than a thickness of the second portion [SP] in the third direction.
Re claim 3, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 2, wherein the contact plug (2240c) includes an upper end portion [UE] in contact with the first bit line, and a width of the upper end portion in the first direction (horizontal) is larger than a width of the upper end portion in the second direction (vertical).
Re claim 4, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 3, wherein a width of the upper end portion in the second direction (width of a little portion on top) decreases as the upper end portion goes up [UE].
Re claim 5, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 2, wherein a width of the first bit line in the second direction decreases (width of a little portion on top of 2371c) as the first bit line goes up.
Re claim 6, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 5, wherein the first bit line includes Cu (copper) [0183].
Re claim 8, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 2, wherein
the contact plug has a column shape extending in the third direction, and a first diameter [FD] of the contact plug close to the first bit line (2271c) is smaller than a second diameter [SD] of the contact plug farther from the first bit line than the first diameter, each of the first diameter and the second diameter being along the second direction.
Re claim 11, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 2, wherein a portion at which each of the plurality of first conductive layers (2350/2350) and the semiconductor layer (CH) included in the pillar intersect functions as a memory cell transistor (MCR, FIG. 22, [0146]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK in view of BABA (Pub. No.: US 2010/0032725) filed in the IDS on 12/06/2023.
Re claim 7, PARK teaches all the limitation of claim 2.
PARK fails to teach the limitation of claim 7.
BABA teaches wherein the plurality of bit lines (BL202, FIG. 23) includes a second bit line (BL201) provided adjacent to the first bit line in the second direction and a third bit line (BL200) provided adjacent to the second bit line in the second direction, and
a lower surface of each of the first bit line (BL202) and the second bit line (BL201) is higher than a lower surface of the third bit line (BL200).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of achieving much higher integration advantageously as taught by BABA, [0007].
Re claim 9, in the combination, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 7, further comprising:
a first insulating layer [FI] including the plurality of bit lines inside, wherein
the plurality of bit lines includes a fourth bit line [FBL] left provided on an opposite side of the second bit line [SBL] with respect to the first bit line, and
a lower surface of the fourth bit line [FBL] is higher than a lower surface of the first insulating layer [FI].
Re claim 10, in the combination, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 7, further comprising: a second insulating layer (2215) provided between the second bit line (2360) and the contact plug (2240c).
Response to Arguments
Applicant's arguments filed 07/02/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument:
“The Office Action asserts that Park discloses bit lines including lower bonding metal 2271c asserted to correspond to the first bit line above a transistor 2220c. The Office Action also asserts that metal layers 2230/2240 correspond to the contact plug. Page 2 of the Office includes a marked-up figure 20 of Park identifying what is asserted to be the first portion (FP) and the second portion (SP). As is clear from the annotated drawing, the asserted first portion FP overlaps the asserted contact plug 2230/2240 in the third direction which corresponds to D1. Thus, the thickness of the first portion being thinner than a thickness of the second portion is with respect to the direction D1 in Park, which corresponds to the third direction in Claim 2.
The portion of layer 2271c corresponding to the first portion FP does not have a thickness thinner than a thickness of the portion of layer 2271c indicated as the second portion SP in the annotated figure. The annotated figure indicates that the first portion is thinner than the second portion in the D2 direction, but this does not correspond to the third direction of Claim 2. As can be seen from Fig 30, the lower portion of 2271c asserted to be FP is thicker in the D1 direction than the upper portion of 2271c asserted to the second portion SP.
Also, the first bit line has a first portion that overlaps the contact plug in the third
direction and a second portion other than the first portion. The portion indicated as SP in the annotated drawing overlaps the second metal layer 2240c in the D1 direction (third direction) and, thus, does not correspond to the second portion of the first bit line recited in Claim 2.
Applicant refers the Examiner to Figs. 4, 7 and 8 as non-limiting examples of features of the device of Claim 2. As shown in Fig. 8, bit line 35_3 extends in the Y-direction and a portion of bit line 35_3 under contact plug 36 is thinner in the Z-direction than other portions of bit line 35_3 located at other positions in the Y-direction. Park does not disclose that a portion of metal layer 2271c in the D3 direction that does not overlap with metal layer 2240c is thinner in the D1 direction than a portion of metal layer 2271c that overlaps with metal layer 2240c.
As Park does not disclose the first bit line with the first and second portions with the recited thicknesses in the third direction, the § 102 rejection over Park should be withdrawn. Claim 2 is patentable over Park.”, pages 3-4.
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The Examiner respectfully submits that because of Applicant did not specify the orientation of the third direct via the first and second direction (like 90º via the first cross sectional cut along the B-B of FIG. 6 in plan-view), therefore, Examiner treated the third direction as another horizontal direction whereat different location and PARK, FIG. 30 [as shown above] still reads on:
the first bit line (2271c) includes a first portion [FP] that overlaps the contact plug in the third direction (horizontal line at different location) and a second portion [SP] other than the first portion, and
a thickness of the first portion [FP] in the third direction (horizontal) is thinner than a thickness of the second portion [SP] in the third direction.
For the above reasons, it is believed that the rejections should be sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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