Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species I. Claims 2-11 in the reply filed on 01/13/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 2-6, 8 and 11 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by PARK (Pub. No.: US 2020/0402579) filed in the IDS on 12/06/2023 . Re claim 2, PARK, FIG. 30 [as shown above] teaches a semiconductor memory device comprising: a substrate (2210) ; a transistor (2220) provided above the substrate; a plurality of bit lines provided above the transistor, each extending in a first direction ( horizontal ) , and arranged in a second direction ( vertical ) intersecting the first direction, the plurality of bit lines including a first bit line (2271c) ; a contact plug (2230/2240) provided below the first bit line, in contact with the first bit line and extending in a third direction perpendicular to the first direction and the second direction; a plurality of first conductive layers (2350/2350) provided above the first bit line and stacked in the third direction; and a pillar (CH) including a semiconductor layer penetrating the plurality of first conductive layers in the third direction and electrically connected to the first bit line, wherein the first bit line (2271 c ) includes a first portion [FP] that overlaps the contact plug in the third direction and a second portion [SP] other than the first portion, and a thickness of the first portion [ FP] in the third direction (looking down from the top) is thinner than a thickness of the second portion in the third direction (SP] . Re claim 3 , PARK, FIG. 30 [as shown above] teaches t he semiconductor memory device according to claim 2, wherein the contact plug (2240c) includes an upper end portion [UE] in contact with the first bit line, and a width of the upper end portion in the first direction (horizontal) is larger than a width of the upper end portion in the second direction (vertical) . Re claim 4 , PARK, FIG. 30 [as shown above] teaches t he semiconductor memory device according to claim 3, wherein a width of the upper end portion in the second direction ( width of a little portion on top) decreases as the upper end portion goes up [UE] . Re claim 5 , PARK, FIG. 30 [as shown above] teaches t he semiconductor memory device according to claim 2, wherein a width of the first bit line in the second direction decreases ( width of a little portion on top of 2371c) as the first bit line goes up. Re claim 6 , PARK, FIG. 30 [as shown above] teaches t he semiconductor memory device according to claim 5, wherein the first bit line includes Cu (copper) [0183] . Re claim 8 , PARK, FIG. 30 [as shown above] teaches t he semiconductor memory device according to claim 2, wherein the contact plug has a column shape extending in the third direction, and a first diameter [FD] of the contact plug close to the first bit line (2271c) is smaller than a second diameter [SD] of the contact plug farther from the first bit line than the first diameter, each of the first diameter and the second diameter being along the second direction. Re claim 11, PARK, FIG. 30 [as shown above] teaches the semiconductor memory device according to claim 2, wherein a portion at which each of the plurality of first conductive layers (2350/2350) and the semiconductor layer (CH) included in the pillar intersect functions as a memory cell transistor (MCR, FIG. 22, [0146]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7, 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK in view of BABA (Pub. No.: US 20 10/0032725 ) filed in the IDS on 12/06/2023 . Re c laim 7, PARK teach es all the limitation of claim 2 . PARK fails to teach the limitation of claim 7. BABA teaches wherein the plurality of bit lines (BL202, FIG. 23) includes a second bit line (BL20 1) provided adjacent to the first bit line in the second direction and a third bit line (BL20 0) provided adjacent to the second bit line in the second direction, and a lower surface of each of the first bit line (BL202 ) and the second bit line (BL20 1) is higher than a lower surface of the third bit line (BL20 0) . I t would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for th e purpose of achiev ing much higher integration advantageously as taught by BABA, [0007] . Re claim 9 , in the combination, PARK, FIG. 30 [as shown above] teaches t he semiconductor memory device according to claim 7, further comprising: a first insulating layer [FI] including the plurality of bit lines inside, wherein the plurality of bit lines includes a fourth bit line [FBL] left provided on an opposite side of the second bit line [SBL] with respect to the first bit line, and a lower surface of the fourth bit line [FBL] is higher than a lower surface of the first insulating layer [FI] . Re claim 10 , in the combination, PARK, FIG. 30 [as shown above] teaches t he semiconductor memory device according to claim 7, further comprising: a second insulating layer (2215) provided between the second bit line (2360) and the contact plug (2240 c ) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT TONY TRAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1749 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 8AM-5PM, EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Britt Hanley can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-3042 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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