Prosecution Insights
Last updated: April 19, 2026
Application No. 18/530,443

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
Dec 06, 2023
Examiner
HUTSON, NICHOLAS LELAND
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Auo Corporation
OA Round
1 (Non-Final)
64%
Grant Probability
Moderate
1-2
OA Rounds
3y 1m
To Grant
68%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allow Rate
9 granted / 14 resolved
-3.7% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
37 currently pending
Career history
51
Total Applications
across all art units

Statute-Specific Performance

§103
53.3%
+13.3% vs TC avg
§102
37.0%
-3.0% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sizov et al (US Publication 20200343230). Regarding claim 1, Sizov teaches a manufacturing method of a display device, comprising: providing a plurality of light emitting diodes (Fig. 3A, 3020) on a first transpose carrier plate (Fig. 3A, 300), wherein each of the light emitting diodes comprises a first electrode (Fig. 3A and 7, 180), a semiconductor stack structure (Fig. 3A and 7, 104, 106, and 108) and a second electrode (Fig. 3B, n-contact, para 64) stacked with each other; forming a plurality of transparent packaging structures respectively on the light emitting diodes (Fig. 3A, 134, para 58-59); forming a molding layer on the first transpose carrier plate, wherein the molding layer is located between adjacent ones of the transparent packaging structures (Fig. Fig. 3A 170/174); forming a redistribution structure at a first side of the molding layer, wherein the redistribution structure is electrically connected to the first electrodes of the light emitting diodes (Fig. 3B, 410/411 and associated traces); connecting a second transpose carrier plate to the redistribution structure (Fig. 3A, 3030, 176), and removing the first transpose carrier plate (Fig. 3B, 3050, 300 removed); forming a common electrode at a second side of the molding layer, wherein the common electrode is electrically connected to the second electrodes of the light emitting diodes (Fig. 3B, 190 connected to n-contacts, para 64); and electrically connecting the redistribution structure to a circuit substrate (Fig. 3B, 402 connected to 180). Regarding claim 2, Sizov teaches the limitations of claim 1 upon which claim 2 depends. Sizov teaches prior to forming the molding layer on the first transpose carrier plate, forming a plurality of reflective structures respectively on the transparent packaging structures (Fig. 3A, 3020, 140). Regarding claim 3, Sizov teaches the limitations of claim 1 upon which claim 3 depends. Sizov teaches forming a plurality of lens structures above the common electrode, wherein the lens structures respectively overlap with the light emitting diodes (Fig. 12A, lens 508 LED 175). Regarding claim 4, Sizov teaches the limitations of claim 1 upon which claim 4 depends. Sizov teaches after forming the common electrode at the second side of the molding layer, connecting a third transpose carrier plate to the common electrode, and removing the second transpose carrier plate; forming a plurality of first conductive terminals and at least one second conductive terminal on the redistribution structure, wherein the first conductive terminals are electrically connected to the first electrodes respectively, and the at least one second conductive terminal is electrically connected to the common electrode; and electrically connecting the redistribution structure to the circuit substrate by the first conductive terminals and the at least one second conductive terminal (Fig. 3A/B, 3030-3040, para 63-64). Regarding claim 5, Sizov teaches the limitations of claim 1 upon which claim 5 depends. Sizov teaches forming a plurality of first covering layers on the first transpose carrier plate, wherein the first covering layers respectively surround the light emitting diodes; and forming a plurality of second covering layers respectively on the first covering layers, wherein each of the transparent packaging structures comprises a corresponding one of the first covering layers and a corresponding one of the second covering layers (Fig. 3A, first covering layer 130, second covering layer 140 - para 57). Regarding claim 6, Sizov teaches a display device, comprising: a circuit substrate (Fig. 7, 400); and at least one light emitting diode packaging structure, electrically connected to the circuit substrate (Fig. 7, plurality of 175 electrically connected to 400), wherein each of the at least one light emitting diode packaging structure comprises: a plurality of light emitting diodes (Fig. 7, plurality of 175), respectively comprising a first electrode (Fig. 7, 180), a semiconductor stack structure (Fig. 7, 104, 106, and 108) and a second electrode (Fig. 3B, n-contact, para 64) stacked with each other; a plurality of transparent packaging structures, respectively surrounding the light emitting diodes (Fig. 3A, 134, para 58-59); a molding layer, surrounding the transparent packaging structures (Fig. 7, 170, para 61-62); a redistribution structure, located on a first side of the molding layer, and electrically connected to the first electrodes of the light emitting diodes (Fig. 3B, 410/411 and associated traces); and a common electrode, located on a second side of the molding layer, and electrically connected to the second electrodes of the light emitting diodes (Fig. 3B, 190). Regarding claim 7, Sizov teaches the limitations of claim Y upon which claim x depends. Sizov teaches a plurality of reflective structures, respectively located on the transparent packaging structures, wherein the reflective structures are located between the molding layer and the transparent packaging structures (Fig. 3A/B, 140, para 60). Regarding claim 8, Sizov teaches the limitations of claim Y upon which claim x depends. Sizov teaches a plurality of lens structures, located above the common electrode, wherein the lens structures respectively overlap with the light emitting diodes (Fig. 12A, lens 508 LED 175). Regarding claim 9, Sizov teaches the limitations of claim Y upon which claim x depends. Sizov teaches wherein each of the at least one transparent double-sided display panel has a plurality of through holes (Fig. 3B and 7, through hole for 420). Regarding claim 10, Sizov teaches the limitations of claim Y upon which claim x depends. Sizov teaches a plurality of first conductive terminals, respectively located on the first conductive structures; and at least one second conductive terminal, located on the at least one second conductive structure (Fig. 3B and 7, 182 and 420 respectively). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeon (US Publication 20240136489) – Display device and manufacturing method thereof. Yoo et al (US Publication 20200013759) – Light emitting element for pixel and led display module. Kang (US Publication 20200168777) – Display device and method of manufacturing the same. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818 /JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Dec 06, 2023
Application Filed
Jan 23, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
64%
Grant Probability
68%
With Interview (+4.2%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allow rate.

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