Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
2. This office action is in response to the filing with the office dated 12/03/2025.
Reply to Applicant’s arguments
3. Applicant’s arguments and claim amendments filed with the office on 12/03/2025 were fully considered and found to be non-persuasive. Applicant’s arguments are directed to amended claim limitations. As per (page 7, paragraph 5) Applicant’s arguments “Claim 1 has been amended with the limitations of claims 3 and 4, and further amended to clarifying that "both the vertical conductive segments and the horizontal conductive segments are embedded in the elastomeric matrix", support for which may be found at least in Fig. 25 of the Application as filed”. Applicant’s amendment introducing the limitation, "both the vertical conductive segments and the horizontal conductive segments are embedded in the elastomeric matrix", changes the scope of the claim, and necessitated the new ground(s) of rejection presented in this Office action.
Regarding Applicant’s arguments about the limitation, “a step of applying a shear stress to incline the layer to incline the vertical conductive segments by an inclination angle with respect to the vertical direction”, with instant specification (paragraphs [0124]-[0126]) as guidance, examiner interprets this limitation, as constraining the elastomeric layer in an inclined structure, as taught by Beaman et al US 5371654 A (line 11-21, column 6). The criss-crossing channels create independent elastomeric columns (shown in FIG. 10 as 138) surrounding the gold wires. This would allow individual wires or groups of wires to compress independently and allow the interposer to compensate for slight variations in the remaining surfaces while reducing the total pressure required to compress the entire interposer (lines 56-68, column 10).
Claims 1, 2, 5-11, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Beaman et al (US 5371654 A) and in view of Higgins (US 5434452A), and Claim 15 is rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Beaman et al (US 5371654 A).
Examiner note: lithography, electrodeposition, liquid deposition, solution deposition and vapor deposition are standard processing methods used in the semiconductor industry to pattern surfaces on wafer. Also see evidence Crippa et al (US 2020/0200795 A1) paragraphs ([0065], [0096], [0097]) and Clayton et al (US 2003/0094666 A1) paragraphs [0069]-[0076]).
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Claim Rejections – 35 U.S.C. 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim 15 is rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Beaman et al (US 5371654 A).
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Regarding independent claim 15, Beaman et al (US 5371654 A) teaches, a method for manufacturing an interface element (element 49, figure 1, element 80, figure 5, lines 26-38, column 6), arranged to put a plurality of terminations of a device to be tested in contact with corresponding channels of a testing head (It is inherent that a semiconductor chip package with interconnect structure and electrical conductors is connected to a test head when it is being tested. Packaging structures for interconnecting electronic devices in a three dimensional structure. More particularly, the present invention is directed to a structure having a plurality of substrates wherein each substrate has a plurality of electronic devices thereon forming an assembly. There are a plurality of assemblies disposed one on top of each other with a vertical wiring interconnection structure disposed between adjacent assemblies. Most particularly, the vertical wire interconnection structure contains a plurality of electrical conductors disposed in an elastomeric material and is compressed between adjacent assemblies (lines 6-18, column 1). The electronic devices 36 and 38 are joined to each thin film wiring layer after the electronic devices are tested and burned in. The electrical interconnection means 49 are fabricated separately and tested. Finally, the stack of assemblies with electronic devices mounted onto the substrates with the electrical interconnection means 49 disposed thereon are aligned and a compressive force is applied to make the interconnections. The force is preferably from 10 to 50 grams per contact or from 70 to 300 kilograms for the entire package, (lines 10-18, column 6), comprising the steps of: a) arranging at least one elastomer layer, which rises vertically from a lower face to an upper face (element 49, figure 1, element 80, figure 5, lines 26-38, column 6); b) forming a plurality of vias which are distinct from each other passing through the elastomer layer from the lower face up to the upper face (channels accommodating element 84 in figures 5, 6); c) filling said vias with a conductive material to form just as many conductive segments (conductor 84 passing through two sides 86 and 88 of an elastomeric material 82 are shown in figures 5 and 6, lines 26-38, column 6); wherein, at the end of the manufacturing method, the layers define an elastomeric matrix extended between an upper face and a lower face which are substantially parallel (element 82, figure 5, lines 26-38, column 6) and spaced apart by a thickness measured along a vertical direction and the conductive segments define conductors provided with at least one portion which is not parallel to the vertical direction (element 82, figure 5, lines 26-38, column 6); wherein the method provides the deposition of a single layer on which vertical vias and vertical conductive segments oriented along the vertical direction are then formed (line 11-21, column 6); the method further comprising a step of applying a shear stress to incline the layer to incline the vertical conductive segments by an inclination angle with respect to the vertical direction (line 11-21, column 6); The criss-crossing channels create independent elastomeric columns (shown in FIG. 10 as 138) surrounding the gold wires. This would allow individual wires or groups of wires to compress independently and allow the interposer to compensate for slight variations in the remaining surfaces while reducing the total pressure required to compress the entire interposer (lines 56-68, column 10).
Regarding the limitation, “a step of applying a shear stress to incline the layer to incline the vertical conductive segments by an inclination angle with respect to the vertical direction”, examiner interprets this limitation, with instant specification (paragraphs [0124]-[0126] as guidance, as constraining the elastomeric layer in an inclined structure, as taught by Beaman et al US 5371654 A (line 11-21, column 6).
Claim Rejections – 35 U.S.C. 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1, 2, 5-11, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Beaman et al (US 5371654 A) and in view of Higgins (US 5434452A).
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Regarding independent claim 1, Beaman et al (US 5371654 A) teaches, An interface element (element 49, figure 1, element 80, figure 5, lines 26-38, column 6) arranged to put a plurality of terminations of a device to be tested in contact with corresponding channels of a testing head (It is inherent that a semiconductor chip package with interconnect structure and electrical conductors is connected to a test head when it is being tested. The electronic devices 36 and 38 are joined to each thin film wiring layer after the electronic devices are tested and burned in. The electrical interconnection means 49 are fabricated separately and tested. Finally, the stack of assemblies with electronic devices mounted onto the substrates with the electrical interconnection means 49 disposed thereon are aligned and a compressive force is applied to make the interconnections. The force is preferably from 10 to 50 grams per contact or from 70 to 300 kilograms for the entire package (lines 10-18, column 6), packaging structures for interconnecting electronic devices in a three dimensional structure. More particularly, the present invention is directed to a structure having a plurality of substrates wherein each substrate has a plurality of electronic devices thereon forming an assembly. There are a plurality of assemblies disposed one on top of each other with a vertical wiring interconnection structure disposed between adjacent assemblies. Most particularly, the vertical wire interconnection structure contains a plurality of electrical conductors disposed in an elastomeric material and is compressed between adjacent assemblies (lines 6-18, column 1). Also see lines 10-18, column 6), comprising: at least one elastomeric matrix (element 82, figure 5, lines 26-38, column 6) and a plurality of conductors embedded (element 84, figure 5, lines 26-38, column 6) in said elastomeric matrix; said interface element having an upper face and a lower face which are substantially parallel and spaced apart by a thickness measured along a vertical direction (figure 5, lines 26-38, column 6); and said conductors are separated from each other and passing through the whole thickness of the interface element from the upper face to the lower face (figure 5, lines 26-38, column 6), said conductors having at least one portion which is not parallel to said vertical direction (figure 5, lines 26-38, column 6).
Beaman et al is silent about, wherein each of said conductors comprises a plurality of conductive segments oriented in a different direction and overlapped in the vertical direction; and wherein said conductive segments are vertical conductive segments, oriented along the vertical direction, alternated with horizontal segments, oriented along a horizontal direction which is parallel to said upper and lower faces, wherein both the vertical conductive segments and the horizontal conductive segments are embedded in the elastomeric matrix.
Higgins (US 5434452A) teaches, wherein each of said conductors comprises a plurality of conductive segments oriented in a different direction and overlapped in the vertical direction (figure 2, 11, lines 4-30, column 3, lines 36-50, column 4); and wherein said conductive segments are vertical conductive segments, oriented along the vertical direction (figure 2, 11,
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lines 4-30, column 3, lines 36-50, column 4), alternated with horizontal segments, oriented along a horizontal direction which is parallel to said upper and lower faces (figure 2, 11, lines 4-30, column 3, lines 36-
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50, column 4), wherein both the vertical conductive segments and the horizontal conductive segments are embedded in the elastomeric matrix (figure 2, 11, lines 4-30, column 3, lines 36-50, column 4).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Beaman et al by providing vertical and horizontal micro-beam conductors as taught by Higgins.
One of the ordinary skill in the art would have been motivated to make such a modification so that a separable compliant connector film or wiring substrate may be used to temporarily or permanently connect two electrical circuit elements, each of which may possess a field of non-planar contact pads, Moreover, this continuous field of connector elements on the wiring substrate allows a degree of misalignment of two circuit elements to be interconnected due to the compliance offered by each of the electrically isolated micro-beam conductor elements, and to provide connector elements or contact bumps in precise locations, as taught by Higgins (lines 47-59, column 6).
Regarding dependent claim 2, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the interface element according to claim 1.
Beaman et al (US 5371654 A) teaches, wherein one of the faces is integrally associated with a substrate (two sides 86 and 88 of an elastomeric material 82 are shown in figures 5 and 6).
Regarding dependent claim 5, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the interface element according to claim 1.
Beaman et al (US 5371654 A) further teaches, wherein said horizontal segments are vertically overlapped, and said vertical segments are vertically overlapped two by two (figures 7 and 8 also see lines 1-27, column 5; Beaman et al and Higgins combined teach the limitations of claim 1. Beaman et al also teaches stack of assemblies with electronic devices mounted onto the substrates with the electrical interconnection means 49 disposed thereon are aligned and a compressive force is applied to make the interconnections. The electrical interconnection means 49 are fabricated separately and tested. Finally, the stack of assemblies with electronic devices mounted onto the substrates with the electrical interconnection means 49 disposed thereon are aligned and a compressive force is applied to make the interconnections; lines 13-18, column 6).
Regarding dependent claim 6, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the interface element according to claim 5.
Beaman et al (US 5371654 A) teaches, wherein said conductors are inclined by an inclination angle with respect to said vertical direction (Figures 5 and 6).
Regarding dependent claim 7, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the interface element according to claim 6.
Beaman et al (US 5371654 A) teaches, wherein said inclination angle is between 15° and 45° (Figures 5 and 6).
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Regarding independent claim 8, Beaman et al (US 5371654 A) teaches, a method for manufacturing an interface element (element 49, figure 1, element 80, figure 5, lines 26-38, column 6) arranged to put a plurality of terminations of a device to be tested in contact with corresponding channels of a testing head (It is inherent that a semiconductor chip package with interconnect structure and electrical conductors is connected to a test head when it is being tested. The electronic devices 36 and 38 are joined to each thin film wiring layer after the electronic devices are tested and burned in. The electrical interconnection means 49 are fabricated separately and tested. Finally, the stack of assemblies with electronic devices mounted onto the substrates with the electrical interconnection means 49 disposed thereon are aligned and a compressive force is applied to make the interconnections. The force is preferably from 10 to 50 grams per contact or from 70 to 300 kilograms for the entire package (lines 10-18, column 6), packaging structures for interconnecting electronic devices in a three dimensional structure. More particularly, the present invention is directed to a structure having a plurality of substrates wherein each substrate has a plurality of electronic devices thereon forming an assembly. There are a plurality of assemblies disposed one on top of each other with a vertical wiring interconnection structure disposed between adjacent assemblies. Most particularly, the vertical wire interconnection structure contains a plurality of electrical conductors disposed in an elastomeric material and is compressed between adjacent assemblies (lines 6-18, column 1). Also
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see lines 10-18, column 6), the method comprising the steps of: arranging at least one elastomer layer which rises vertically from a lower face to an upper face (element 49, figure 1, element 80, figure 5, lines 26-38, column 6); forming a plurality of vias (channels accommodating element 84 in figures 5, 6) which are distinct from each other passing through the elastomer layer from the lower face up to the upper face (conductor 84 passing through two sides 86 and 88 of an elastomeric material 82 are shown in figures 5 and 6, lines 26-38, column 6); and filling said vias with a conductive material to form just as many conductive segments (conductor 84 passing through two sides 86 and 88 of an elastomeric material 82 are shown in figures 5 and 6, lines 26-38, column 6); wherein steps (a, b, c) are repeated to form a plurality of layers (figure 4) and wherein, at an end of the manufacturing method, the layers define an elastomeric matrix extended between an upper face and a lower face which are substantially parallel (element 82, figure 5, lines 26-38, column 6) and spaced apart by a thickness measured along a vertical direction and the conductive segments define conductors provided with at least one portion which is not parallel to the vertical direction (element 82, figure 5, lines 26-38, column 6).
Beaman et al is silent about the conductive segments corresponding to successive layers being oriented in different directions and connected to form a broken line.
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Higgins (US 5434452A) teaches, the conductive segments corresponding to successive layers being oriented in different directions and connected to form a broken line (figure 2, 11, lines 4-30, column 3) (A compliant integrated circuit (IC) wiring substrate (10) has an insulative carrier film (14) and a plurality of micro-beam conductors (12) in the carrier film. Each of the plurality of micro-beam conductors has a pair of contact bumps (16 and 18) connected to respective posts (22 and 24). A beam element (20) connects the pair of contact bumps and posts at opposing ends and opposing surfaces of the beam element. The plurality of micro-beam conductors extend through the thickness of the carrier film such that the pair of contact bumps protrude from the opposite surfaces of the carrier film. The compliance of the wiring substrate can be varied by varying locations of apertures in the insulative carrier film (abstract). FIG. 1 illustrates, in a partial top view, a mechanical IC wiring substrate 10 showing a field of z-axis compliant conductors 12 in accordance with an embodiment of the present invention. The compliant mechanical IC wiring substrate is composed of a plurality of micro-beam conductors 12 embedded in, or on, an insulating carrier film 14. The carrier film 14 can be of a variety of nonconductive or insulating materials, such as polyimide, polyester, polystyrene, polyethylene, epoxy resins, urethane, polycarbonate, and silicone. However, the carrier film 14 is in no way limited to the listed materials as other insulating materials may also be suitable for providing the carrier film. The plurality of micro-beam conductors 12 is cantilevered to provide compliance in the z-axis, in contrast to the conductors in the prior art. As illustrated in FIG. 1, each micro-beam conductor 12 has two contact bumps 16 and 18 which are offset from each other. Each pair of contact bumps is connected by a beam element 20. The dotted lines in FIG. 1 represent hidden lines. The beam elements 20 are embedded in the bulk material of the carrier film 14, and the contact bumps 16 protrude from the bottom surface of the carrier film. The contact bumps 18 protrude from the top surface of the carrier film. This feature is more easily understood in a cross-sectional view along line 2--2 which is illustrated in FIG. 2. (lines 4-30, column 3).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Beaman et al by providing vertical and horizontal micro-beam conductors as taught by Higgins.
One of the ordinary skill in the art would have been motivated to make such a modification so that a separable compliant connector film or wiring substrate may be used to temporarily or permanently connect two electrical circuit elements, each of which may possess a field of non-planar contact pads, allowing a degree of misalignment of two circuit elements to be interconnected due to the compliance offered by each of the electrically isolated micro-beam conductor elements, and to provide connector elements or contact bumps in precise locations, as taught by Higgins (lines 47-59, column 6).
Regarding dependent claim 9, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the method for manufacturing an interface element according to claim 8.
Beaman et al (US 5371654 A) further teaches wherein a first elastomer layer is deposited and cured directly on a substrate (lines 18-23, column 9, lines 38-47, column 10).
Regarding dependent claim 10, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the method for manufacturing an interface element according to claim 8.
Beaman et al (US 5371654 A) further teaches, wherein the step of forming said vias is performed according to a photolithographic process and provides a sub-step of imprinting by radiation the elastomer layer and a following sub-step of removing the imprinted material (Also, the surface of the copper sacrificial substrate can be textured or embossed prior to gold plating and wire bonding to provide a textured or raised contact surface on the bottom of the ball bonds. The completed interposer 218 of FIG. 21 can be further modified by using a laser to scribe channels in the elastomeric material between the bond wires at an angle matching the angle of the bond wires, as shown in FIG. 7 (lines 49-56, column 10); Grooves have been fabricated with laser, electron beam, metal mask and slicing with a blade. Other techniques such as stamping, injection molding and other known techniques to create the desired geometry would also work well (lines 9-13, column 11) and removal of the low molecular weight-side products (fabrication details in figures 11-19 and their description in columns 8 and 9).
Examiner note: lithography, electrodeposition, liquid deposition, solution deposition and vapor deposition are standard processing methods used in the semiconductor industry to pattern surfaces on wafer. Also see evidence Crippa et al (US 2020/0200795 A1) paragraphs ([0065], [0096], [0097]) and Clayton et al (US 2003/0094666 A1) paragraphs [0069]-[0076]).
Regarding dependent claim 11, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the method for manufacturing an interface element according to claim 8.
Beaman et al (US 5371654 A) further teaches, wherein said step of filling said vias uses galvanic deposition of a metal conductor (lines 49-56, column 10; lines 9-13, column 11, figures 11-19 and their description in columns 8 and 9).
Examiner note: lithography, electrodeposition, liquid deposition, solution deposition and vapor deposition are standard processing methods used in the semiconductor industry to pattern surfaces on wafer. Also see evidence Crippa et al (US 2020/0200795 A1) paragraphs [0065], [0096], [0097]) and Clayton et al (US 2003/0094666 A1) paragraphs [0069]-[0076]).
Regarding dependent claim 13, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the method for manufacturing an interface element according to claim 8.
Higgins (US 5434452A) further teaches, wherein said layers comprise thicker layers alternated with less thick layers; the vias formed at the thicker layers are vertical vias whose extension in the vertical direction prevails with respect to the extension in the horizontal direction (figures 2 and 11, lines 4-30, column 3, The height of the posts 22 and 24 can range from 20 .mu.m to 30 .mu.m. Additionally, the thickness of the beam element 20 can range from 10 .mu.m to 15 .mu.m. (lines 23-26, column 4); the vias formed at the less thick layers being
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horizontal vias whose extension in the horizontal direction prevails with respect to the extension in the vertical direction (figures 2 and 11, lines 4-30, column 3; The height of the posts 22 and 24 can range from 20 .mu.m to 30 .mu.m. Additionally, the thickness of the beam element 20 can range from 10 .mu.m to 15 .mu.m. (lines 23-26, column 4); and the corresponding conductive segments are vertical segments and horizontal segments respectively (figures 2 and 11, lines 4-30, column 3; The height of the posts 22 and 24 can range from 20 .mu.m to 30 .mu.m. Additionally, the thickness of the beam element 20 can range from 10 .mu.m to 15 .mu.m. (lines 23-26, column 4); A compliant integrated circuit (IC) wiring substrate (10) has an insulative carrier film (14) and a plurality of micro-beam conductors
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(12) in the carrier film. Each of the plurality of micro-beam conductors has a pair of contact bumps (16 and 18) connected to respective posts (22 and 24). A beam element (20) connects the pair of contact bumps and posts at opposing ends and opposing surfaces of the beam element. The plurality of micro-beam conductors extend through the thickness of the carrier film such that the pair of contact bumps protrude from the opposite surfaces of the carrier film. The compliance of the wiring substrate can be varied by varying locations of apertures in the insulative carrier film (abstract). FIG. 1 illustrates, in a partial top view, a mechanical IC wiring substrate 10 showing a field of z-axis compliant conductors 12 in accordance with an embodiment of the present invention. The compliant mechanical IC wiring substrate is composed of a plurality of micro-beam conductors 12 embedded in, or on, an insulating carrier film 14. The carrier film 14 can be of a variety of nonconductive or insulating materials, such as polyimide, polyester, polystyrene, polyethylene, epoxy resins, urethane, polycarbonate, and silicone. However, the carrier film 14 is in no way limited to the listed materials as other insulating materials may also be suitable for providing the carrier film. The plurality of micro-beam conductors 12 is cantilevered to provide compliance in the z-axis, in contrast to the conductors in the prior art. As illustrated in FIG. 1, each micro-beam conductor 12 has two contact bumps 16 and 18 which are offset from each other. Each pair of contact bumps is connected by a beam element 20. The dotted lines in FIG. 1 represent hidden lines. The beam elements 20 are embedded in the bulk material of the carrier film 14, and the contact bumps 16 protrude from the bottom surface of the carrier film. The contact bumps 18 protrude from the top surface of the carrier film. This feature is more easily understood in a cross-sectional view along line 2--2 which is illustrated in FIG. 2. (lines 4-30, column 3).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Beaman et al by providing vertical and horizontal micro-beam conductors as taught by Higgins.
One of the ordinary skill in the art would have been motivated to make such a modification so that a separable compliant connector film or wiring substrate may be used to temporarily or permanently connect two electrical circuit elements, each of which may possess a field of non-planar contact pads, allowing a degree of misalignment of two circuit elements to be interconnected due to the compliance offered by each of the electrically isolated micro-beam conductor elements, and to provide connector elements or contact bumps in precise locations, as taught by Higgins (lines 47-59, column 6).
Regarding dependent claim 14, Beaman et al (US 5371654 A) and Higgins (US 5434452A) teach, the method for manufacturing an interface element according to claim 13.
Beaman et al (US 5371654 A) and Higgins (US 5434452A) further combined teach, wherein said horizontal vias are vertically overlapped, and said vertical vias are vertically overlapped two by two (figures 5-8 also see lines 1-27, column 5; Beaman et al and Higgins combined teach the limitations of claim 1. Beaman et al also teaches stack of assemblies with electronic devices mounted onto the substrates with the electrical interconnection means 49 disposed thereon are aligned and a compressive force is applied to make the interconnections. The electrical interconnection means 49 are fabricated separately and tested. Finally, the stack of assemblies with electronic devices mounted onto the substrates with the electrical interconnection means 49 disposed thereon are aligned and a compressive force is applied to make the interconnections (lines 13-18, column 6).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Beaman et al by providing multiple layers of overlapped vertical and horizontal micro-beam conductors as taught by Higgins.
One of the ordinary skill in the art would have been motivated to make such a modification so that a separable compliant connector film or wiring substrate may be used to temporarily or permanently connect two electrical circuit elements, each of which may possess a field of non-planar contact pads, allowing a degree of misalignment of two circuit elements to be interconnected due to the compliance offered by each of the electrically isolated micro-beam conductor elements, and to provide connector elements or contact bumps in precise locations, as taught by Higgins (lines 47-59, column 6).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURESH RAJAPUTRA whose telephone number is (571) 270-0477. The examiner can normally be reached between 8:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached on 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SURESH K RAJAPUTRA/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 3/9/2026